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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:16 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:16 +0100 |
| commit | 6efa660124f481a5ba415cedd195764ea6ac09fd (patch) | |
| tree | 5ceb8e36ccb0439e3256688ff9cfb98abb06673d /opcodes/aarch64-dis.h | |
| parent | ce623e7aa486d1330c9a4529c77a302d2fdcb801 (diff) | |
| download | binutils-gdb-6efa660124f481a5ba415cedd195764ea6ac09fd.tar.gz | |
aarch64: Add the SME2 shift instructions
There are two instruction formats here:
- SQRSHR, SQRSHRU and UQRSHR, which operate on lists of two
or four registers.
- SQRSHRN, SQRSHRUN and UQRSHRN, which operate on lists of
four registers.
These are the first SME2 instructions to have immediate operands.
The patch makes sure that, when parsing SME2 instructions with
immediate operands, the new predicate-as-counter registers are
parsed as registers rather than as #-less immediates.
Diffstat (limited to 'opcodes/aarch64-dis.h')
| -rw-r--r-- | opcodes/aarch64-dis.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h index 6e6c00b1de2..3be382fe5fd 100644 --- a/opcodes/aarch64-dis.h +++ b/opcodes/aarch64-dis.h @@ -135,6 +135,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1); AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2); AARCH64_DECL_OPD_EXTRACTOR (ext_x0_to_x30); AARCH64_DECL_OPD_EXTRACTOR (ext_simple_index); +AARCH64_DECL_OPD_EXTRACTOR (ext_plain_shrimm); #undef AARCH64_DECL_OPD_EXTRACTOR |