[AArch64][SVE 26/32] Add SVE MUL VL addressing modes

This patch adds support for addresses of the form:

       [<base>, #<offset>, MUL VL]

This involves adding a new AARCH64_MOD_MUL_VL modifier, which is
why I split it out from the other addressing modes.

For LD2, LD3 and LD4, the offset must be a multiple of the structure
size, so for LD3 the possible values are 0, 3, 6, ....  The patch
therefore extends value_aligned_p to handle non-power-of-2 alignments.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
	(AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
	(AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
	(AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
	(AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
	operands.
	* aarch64-opc.c (aarch64_operand_modifiers): Initialize
	the AARCH64_MOD_MUL_VL entry.
	(value_aligned_p): Cope with non-power-of-two alignments.
	(operand_general_constraint_met_p): Handle the new MUL VL addresses.
	(print_immediate_offset_address): Likewise.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
	(ins_sve_addr_ri_s9xvl): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
	(aarch64_ins_sve_addr_ri_s6xvl): Likewise.
	(aarch64_ins_sve_addr_ri_s9xvl): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
	(ext_sve_addr_ri_s9xvl): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
	(aarch64_ext_sve_addr_ri_s4xvl): Likewise.
	(aarch64_ext_sve_addr_ri_s6xvl): Likewise.
	(aarch64_ext_sve_addr_ri_s9xvl): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
	parse_shift_modes.
	(parse_shift): Handle SHIFTED_MUL_VL.
	(parse_address_main): Add an imm_shift_mode parameter.
	(parse_address, parse_sve_address): Update accordingly.
	(parse_operands): Handle MUL VL addressing modes.

1 files changed, 3 insertions, 0 deletions

diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h
index 0ce2d8930d0..5619877be54 100644
--- a/opcodes/aarch64-dis.h
+++ b/opcodes/aarch64-dis.h
@@ -91,6 +91,9 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_hint);
 AARCH64_DECL_OPD_EXTRACTOR (ext_prfop);
 AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended);
 AARCH64_DECL_OPD_EXTRACTOR (ext_reg_shifted);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4xvl);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s6xvl);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s9xvl);
 AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_u6);
 AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_rr_lsl);
 AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_rz_xtw);