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| author | Faraz Shahbazker <fshahbazker@wavecomp.com> | 2019-04-28 18:21:00 -0700 |
|---|---|---|
| committer | Faraz Shahbazker <fshahbazker@wavecomp.com> | 2019-05-06 06:43:32 -0700 |
| commit | 41cee0897b670168e0d6f455c9bc45c73f8023df (patch) | |
| tree | 90f15ebdf438ae1956dc5a3d7eea35c64ae41a10 /opcodes/mips-dis.c | |
| parent | be0d3bbbcdbdba83f74d8ad1be6c4c759255af0b (diff) | |
| download | binutils-gdb-41cee0897b670168e0d6f455c9bc45c73f8023df.tar.gz | |
Add load-link, store-conditional paired EVA instructions
Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1]. These instructions are optional within
the EVA ASE. Their presence is indicated by the XNP bit in the
Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 230-231, pp. 357-360.
gas/
* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
(mips_after_parse_args): Translate EVA to EVA_R6.
* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
* testsuite/gas/mips/eva.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Check errors for
new instructions.
* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
include/
* opcode/mips.h (ASE_EVA_R6): New macro.
(M_LLWPE_AB, M_SCWPE_AB): New enum values.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Add ISA
argument and set ASE_EVA_R6 appropriately.
(set_default_mips_dis_options): Pass ISA to above.
(parse_mips_dis_option): Likewise.
* mips-opc.c (EVAR6): New macro.
(mips_builtin_opcodes): Add llwpe, scwpe.
Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
Diffstat (limited to 'opcodes/mips-dis.c')
| -rw-r--r-- | opcodes/mips-dis.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 0dc437ede47..5bf33d9f8fd 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -829,7 +829,7 @@ mips_convert_abiflags_ases (unsigned long afl_ases) /* Calculate combination ASE flags from regular ASE flags. */ static unsigned long -mips_calculate_combination_ases (unsigned long opcode_ases) +mips_calculate_combination_ases (int opcode_isa, unsigned long opcode_ases) { unsigned long combination_ases = 0; @@ -837,6 +837,10 @@ mips_calculate_combination_ases (unsigned long opcode_ases) combination_ases |= ASE_XPA_VIRT; if ((opcode_ases & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) combination_ases |= ASE_MIPS16E2_MT; + if ((opcode_ases & ASE_EVA) + && ((opcode_isa & INSN_ISA_MASK) == ISA_MIPS64R6 + || (opcode_isa & INSN_ISA_MASK) == ISA_MIPS32R6)) + combination_ases |= ASE_EVA_R6; return combination_ases; } @@ -909,7 +913,7 @@ set_default_mips_dis_options (struct disassemble_info *info) mips_ase |= ASE_MDMX; } #endif - mips_ase |= mips_calculate_combination_ases (mips_ase); + mips_ase |= mips_calculate_combination_ases (mips_isa, mips_ase); } /* Parse an ASE disassembler option and set the corresponding global @@ -997,7 +1001,7 @@ parse_mips_dis_option (const char *option, unsigned int len) if (parse_mips_ase_option (option)) { - mips_ase |= mips_calculate_combination_ases (mips_ase); + mips_ase |= mips_calculate_combination_ases (mips_isa, mips_ase); return; } |