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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-11-13 16:59:21 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2022-11-17 16:43:55 +0800 |
| commit | 01804a098dea7d08857eee82bcaad04676dd8ea1 (patch) | |
| tree | 69ec5662e29df0e9632fca8f788acb0383440ef2 /opcodes/riscv-opc.c | |
| parent | 4a3bc79bf4c0e89c876c930a1e95a02213277460 (diff) | |
| download | binutils-gdb-01804a098dea7d08857eee82bcaad04676dd8ea1.tar.gz | |
RISC-V: Add T-Head Int vendor extension
This patch adds the XTheadInt extension, which provides interrupt
stack management instructions.
The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'opcodes/riscv-opc.c')
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index dfd508b0e71..0e691544f9b 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1935,6 +1935,10 @@ const struct riscv_opcode riscv_opcodes[] = {"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0}, {"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadInt instructions. */ +{"th.ipop", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPOP, MASK_TH_IPOP, match_opcode, 0}, +{"th.ipush", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPUSH, MASK_TH_IPUSH, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadMemIdx instructions. */ {"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0}, {"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, 0}, |