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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-01-11 19:14:02 +0900 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2022-03-18 15:32:22 +0800 |
| commit | 41d6ac5da655a2e78109848f2db47e53552fd61a (patch) | |
| tree | 2d6c789b0169492700e80edbde84342c9c4bb68c /opcodes/riscv-opc.c | |
| parent | 3b374308d3006407b9571e573e4ccce4e904a4c4 (diff) | |
| download | binutils-gdb-41d6ac5da655a2e78109848f2db47e53552fd61a.tar.gz | |
RISC-V: Cache management instructions
This commit adds 'Zicbom' / 'Zicboz' instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction classes.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add cache-block management
instructions.
Diffstat (limited to 'opcodes/riscv-opc.c')
| -rw-r--r-- | opcodes/riscv-opc.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6a288987358..523d1652267 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -852,6 +852,12 @@ const struct riscv_opcode riscv_opcodes[] = {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, +/* Zicbom and Zicboz instructions. */ +{"cbo.clean", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 }, +{"cbo.flush", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 }, +{"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 }, +{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 }, + /* Zbb or zbkb instructions. */ {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 }, {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 }, |