sim: testsuite: flatten tree

Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.

We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim".  Since we have no
other dirs in this tree, and no plans to add any, should be fine.

1 files changed, 126 insertions, 0 deletions

diff --git a/sim/testsuite/m32r/ChangeLog b/sim/testsuite/m32r/ChangeLog
new file mode 100644
index 00000000000..3e6dbf713a3
--- /dev/null
+++ b/sim/testsuite/m32r/ChangeLog
@@ -0,0 +1,126 @@
+2021-01-15  Mike Frysinger  <vapier@gentoo.org>
+
+	* exit47.ms: New testcase from ../../m32r-elf/.
+
+1999-04-21  Doug Evans  <devans@casey.cygnus.com>
+
+	* nop.cgs: Add missing nop insn.
+
+1999-01-05  Doug Evans  <devans@casey.cygnus.com>
+
+	* allinsn.exp: Set all_machs.
+	* misc.exp: Likewise.
+
+1998-12-14  Doug Evans  <devans@casey.cygnus.com>
+
+	* hello.ms: Add trailing \n to expected output.
+	* hw-trap.ms: Ditto.
+
+	* trap.cgs: Properly align trap2_handler.
+
+	* uread16.ms: New testcase.
+	* uread32.ms: New testcase.
+	* uwrite16.ms: New testcase.
+	* uwrite32.ms: New testcase.
+
+Tue Sep 15 14:56:22 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* testutils.inc (test_h_gr): Use mvaddr_h_gr.
+	* rte.cgs: Test bbpc,bbpsw.
+	* trap.cgs: Test bbpc,bbpsw.
+
+Wed Jul  1 15:57:54 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* hw-trap.ms: New testcase.
+
+Wed Jun 10 10:53:20 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* addx.cgs: Add another test.
+	* jmp.cgs: Add another test.
+
+Mon Jun  8 16:08:27 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* trap.cgs: Test trap 2.
+
+Tue Apr 21 10:49:03 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* addx.cgs: Test (-1)+(-1)+1.
+
+Fri Apr 17 16:00:52 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* mv[ft]achi.cgs: Fix expected result
+	(sign extension of top 8 bits).
+
+Fri Feb 20 11:00:02 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* unlock.cgs: Fixed test.
+	* mvfc.cgs: Fixed test.
+	* remu.cgs: Fixed test.
+	* bnc24.cgs: Test long BNC instruction.
+	* bnc8.cgs: Test short BNC instruction.
+	* ld-plus.cgs: Test LD instruction.
+	* macwhi.cgs: Test MACWHI instruction.
+	* macwlo.cgs: Test MACWLO instruction.
+	* mulwhi.cgs: Test MULWHI instruction.
+	* mulwlo.cgs: Test MULWLO instruction.
+	* mvfachi.cgs: Test MVFACHI instruction.
+	* mvfaclo.cgs: Test MVFACLO instruction.
+	* mvtaclo.cgs: Test MVTACLO instruction.
+	* addv.cgs: Test ADDV instruction.
+	* addv3.cgs: Test ADDV3 instruction.
+	* addx.cgs: Test ADDX instruction.
+	* lock.cgs: Test LOCK instruction.
+	* neg.cgs: Test NEG instruction.
+	* not.cgs: Test NOT instruction.
+	* unlock.cgs: Test UNLOCK instruction.
+
+Thu Feb 19 11:15:45 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* testutils.inc (mvaddr_h_gr): new macro to load an
+	address into a general register.
+
+	* or3.cgs: Test OR3 instruction.
+	* rach.cgs: Test RACH instruction.
+	* rem.cgs: Test REM instruction.
+	* sub.cgs: Test SUB instruction.
+	* mv.cgs: Test MV instruction.
+	* mul.cgs: Test MUL instruction.
+	* bl24.cgs: Test long BL instruction.
+	* bl8.cgs: Test short BL instruction.
+	* blez.cgs: Test BLEZ instruction.
+	* bltz.cgs: Test BLTZ instruction.
+	* bne.cgs: Test BNE instruction.
+	* bnez.cgs: Test BNEZ instruction.
+	* bra24.cgs: Test long BRA instruction.
+	* bra8.cgs: Test short BRA instruction.
+	* jl.cgs: Test JL instruction.
+	* or.cgs: Test OR instruction.
+	* jmp.cgs: Test JMP instruction.
+	* and.cgs: Test AND instruction.
+	* and3.cgs: Test AND3 instruction.
+	* beq.cgs: Test BEQ instruction.
+	* beqz.cgs: Test BEQZ instruction.
+	* bgez.cgs: Test BGEZ instruction.
+	* bgtz.cgs: Test BGTZ instruction.
+	* cmp.cgs: Test CMP instruction.
+	* cmpi.cgs: Test CMPI instruction.
+	* cmpu.cgs: Test CMPU instruction.
+	* cmpui.cgs: Test CMPUI instruction.
+	* div.cgs: Test DIV instruction.
+	* divu.cgs: Test DIVU instruction.
+	* cmpeq.cgs: Test CMPEQ instruction.
+	* sll.cgs: Test SLL instruction.
+	* sll3.cgs: Test SLL3 instruction.
+	* slli.cgs: Test SLLI instruction.
+	* sra.cgs: Test SRA instruction.
+	* sra3.cgs: Test SRA3 instruction.
+	* srai.cgs: Test SRAI instruction.
+	* srl.cgs: Test SRL instruction.
+	* srl3.cgs: Test SRL3 instruction.
+	* srli.cgs: Test SRLI instruction.
+	* xor3.cgs: Test XOR3 instruction.
+	* xor.cgs: Test XOR instruction.
+
+Tue Feb 17 12:46:05 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* *: m32r dejagnu simulator testsuite.