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| author | Mike Frysinger <vapier@gentoo.org> | 2021-01-05 22:09:57 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-01-15 19:18:34 -0500 |
| commit | 1368b914e93a3af332f787d3d41c106d11bb90da (patch) | |
| tree | 9893ccae5d2d8cbf2ce855e09d6b8f30b56a21bc /sim/testsuite/sh/bld.s | |
| parent | e403a898b5893337baea73bcb001ece74042f351 (diff) | |
| download | binutils-gdb-1368b914e93a3af332f787d3d41c106d11bb90da.tar.gz | |
sim: testsuite: flatten tree
Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.
We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim". Since we have no
other dirs in this tree, and no plans to add any, should be fine.
Diffstat (limited to 'sim/testsuite/sh/bld.s')
| -rw-r--r-- | sim/testsuite/sh/bld.s | 121 |
1 files changed, 121 insertions, 0 deletions
diff --git a/sim/testsuite/sh/bld.s b/sim/testsuite/sh/bld.s new file mode 100644 index 00000000000..172718df676 --- /dev/null +++ b/sim/testsuite/sh/bld.s @@ -0,0 +1,121 @@ +# sh testcase for bld +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + .align 2 +_x: .long 0xa5a5a5a5 +_y: .long 0x55555555 + + start + +bld_b_imm_disp12_reg: + set_grs_a5a5 + mov.l x, r1 + + bld.b #0, @(0, r1) + bf8k mfail + bld.b #1, @(0, r1) + bt8k mfail + bld.b #2, @(0, r1) + bf8k mfail + bld.b #3, @(0, r1) + bt8k mfail + + bld.b #4, @(0, r1) + bt8k mfail + bld.b #5, @(0, r1) + bf8k mfail + bld.b #6, @(0, r1) + bt8k mfail + bld.b #7, @(0, r1) + bf8k mfail + + bld.b #0, @(1, r1) + bf8k mfail + bld.b #1, @(1, r1) + bt8k mfail + bld.b #2, @(1, r1) + bf8k mfail + bld.b #3, @(1, r1) + bt8k mfail + + bld.b #4, @(1, r1) + bt8k mfail + bld.b #5, @(1, r1) + bf8k mfail + bld.b #6, @(1, r1) + bt8k mfail + bld.b #7, @(1, r1) + bf8k mfail + + bld.b #0, @(2, r1) + bf8k mfail + bld.b #1, @(2, r1) + bt8k mfail + bld.b #2, @(2, r1) + bf8k mfail + bld.b #3, @(2, r1) + bt8k mfail + + bld.b #4, @(2, r1) + bt8k mfail + bld.b #5, @(2, r1) + bf8k mfail + bld.b #6, @(2, r1) + bt8k mfail + bld.b #7, @(2, r1) + bf8k mfail + + bld.b #0, @(3, r1) + bf8k mfail + bld.b #1, @(3, r1) + bt8k mfail + bld.b #2, @(3, r1) + bf8k mfail + bld.b #3, @(3, r1) + bt8k mfail + + bld.b #4, @(3, r1) + bt8k mfail + bld.b #5, @(3, r1) + bf8k mfail + bld.b #6, @(3, r1) + bt8k mfail + bld.b #7, @(3, r1) + bf8k mfail + + assertreg _x, r1 + +bld_imm_reg: + set_greg 0xa5a5a5a5, r1 + bld #0, r1 + bf8k mfail + bld #1, r1 + bt8k mfail + bld #2, r1 + bf8k mfail + bld #3, r1 + bt8k mfail + + bld #4, r1 + bt8k mfail + bld #5, r1 + bf8k mfail + bld #6, r1 + bt8k mfail + bld #7, r1 + bf8k mfail + + test_grs_a5a5 + + pass + + exit 0 + + .align 2 +x: .long _x +y: .long _y + |