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| author | DJ Delorie <dj@redhat.com> | 2008-02-06 00:40:05 +0000 |
|---|---|---|
| committer | DJ Delorie <dj@redhat.com> | 2008-02-06 00:40:05 +0000 |
| commit | c5fbc25baf8de20a337383d4785dd4e15da428b0 (patch) | |
| tree | 949d697d1bf9d65ba3a3bbabde25ec43fe9c9c49 /sim/testsuite/sim/v850/sar.cgs | |
| parent | e5c4eb7a6c1d03decdb318b5a9e43719f207f460 (diff) | |
| download | binutils-gdb-c5fbc25baf8de20a337383d4785dd4e15da428b0.tar.gz | |
Index: ChangeLog
* configure.ac (v850): V850 now has a testsuite.
* configure (v850): Likewise.
Index: testsuite/ChangeLog
* sim/v850/: New directory.
* sim/v850/allinsns.exp: New.
* sim/v850/bsh.cgs: New.
* sim/v850/div.cgs: New.
* sim/v850/divh.cgs: New.
* sim/v850/divh_3.cgs: New.
* sim/v850/divhu.cgs: New.
* sim/v850/divu.cgs: New.
* sim/v850/sar.cgs: New.
* sim/v850/satadd.cgs: New.
* sim/v850/satsub.cgs: New.
* sim/v850/satsubi.cgs: New.
* sim/v850/satsubr.cgs: New.
* sim/v850/shl.cgs: New.
* sim/v850/shr.cgs: New.
* sim/v850/testutils.cgs: New.
* sim/v850/testutils.inc: New.
Index: v850/ChangeLog
* simops.c (OP_C0): Correct saturation logic.
(OP_220): Likewise.
(OP_A0): Likewise.
(OP_660): Likewise.
(OP_80): Likewise.
* simops.c (OP_2A0): If the shift count is zero, clear the
carry.
(OP_A007E0): Likewise.
(OP_2C0): Likewise.
(OP_C007E0): Likewise.
(OP_280): Likewise.
(OP_8007E0): Likewise.
* simops.c (OP_2C207E0): Correct PSW flags for special divu
conditions.
(OP_2C007E0): Likewise, for div.
(OP_28207E0): Likewise, for divhu.
(OP_28007E0): Likewise, for divh. Also, sign-extend the correct
operand.
* v850.igen (divh): Likewise, for 2-op divh.
* v850.igen (bsh): Fix carry logic.
Diffstat (limited to 'sim/testsuite/sim/v850/sar.cgs')
| -rw-r--r-- | sim/testsuite/sim/v850/sar.cgs | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/sim/testsuite/sim/v850/sar.cgs b/sim/testsuite/sim/v850/sar.cgs new file mode 100644 index 00000000000..4372e6c1adb --- /dev/null +++ b/sim/testsuite/sim/v850/sar.cgs @@ -0,0 +1,91 @@ +# v850 sar +# mach: all + + .include "testutils.inc" + +# CY is set to 1 if the bit shifted out last is 1, else 0 +# OV is set to zero. +# Z is set if the result is 0, else 0 + + noflags + seti 4, r1 + seti 0x00000000, r2 + sar r1, r2 + + flags z + reg r2, 0 + + noflags + seti 4, r1 + seti 0x00000001, r2 + sar r1, r2 + + flags z + reg r2, 0 + + noflags + seti 4, r1 + seti 0x00000008, r2 + sar r1, r2 + + flags c + z + reg r2, 0 + + noflags + seti 0x00000000, r2 + sar 4, r2 + + flags z + reg r2, 0 + + noflags + seti 0x00000001, r2 + sar 4, r2 + + flags z + reg r2, 0 + + noflags + seti 0x00000008, r2 + sar 4, r2 + + flags c + z + reg r2, 0 + +# However, if the number of shifts is 0, CY is 0. + + noflags + seti 0, r1 + seti 0xffffffff, r2 + sar r1, r2 + + flags s + reg r2, 0xffffffff + + noflags + seti 0xffffffff, r2 + sar 0, r2 + + flags s + reg r2, 0xffffffff + +# Old MSB is copied as new MSB after shift +# S is 1 if the result is negative, else 0 + + noflags + seti 1, r1 + seti 0x80000000, r2 + sar r1, r2 + + flags s + reg r2, 0xc0000000 + + noflags + seti 1, r1 + seti 0x40000000, r2 + sar r1, r2 + + flags 0 + reg r2, 0x20000000 + + pass |