sim: bfin: fix thinko in SIC pin encoding

When encoding the SIC/pin info into unique input port ids, I used bases
of 100 when I meant to use 0x100.  Rather than simply fix the decoding
math in the different functions, create a few helper macros to simplify
the SIC/pin encoding and decoding steps.  This makes the resulting tables
nice & clear.

And now that pins are clear, the 533 and 537 port_event handlers may
easily be merged into one.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

2 files changed, 516 insertions, 511 deletions

diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog
index 95e05f8c53c..343e67dea08 100644
--- a/sim/bfin/ChangeLog
+++ b/sim/bfin/ChangeLog
@@ -1,3 +1,17 @@
+2011-03-23  Mike Frysinger  <vapier@gentoo.org>
+
+	* dv-bfin_sic.c (ENC, DEC_PIN, DEC_SIC): Define.
+	(bfin_sic_50x_ports, bfin_sic_51x_ports, bfin_sic_52x_ports,
+	bfin_sic_533_ports, bfin_sic_537_ports, bfin_sic_538_ports,
+	bfin_sic_54x_ports, bfin_sic_561_ports, bfin_sic_59x_ports):
+	Encode ids with the ENC macro.
+	(bfin_sic_52x_port_event, bfin_sic_537_port_event,
+	bfin_sic_54x_port_event, bfin_sic_561_port_event): Set idx
+	from my_port with DEC_SIC, and set bit from my_port with DEC_PIN.
+	(bfin_sic_533_port_event): Delete.
+	(bfin_sic_finish): Call set_hw_port_event with
+	bfin_sic_537_port_event for BF533 and BF59x targets.
+
 2011-03-23  Robin Getz  <robin.getz@analog.com>
 
 	* bfin-sim.c (decode_dsp32alu_0): Drop the src0/src1 check for
diff --git a/sim/bfin/dv-bfin_sic.c b/sim/bfin/dv-bfin_sic.c
index 3df7ffb6298..f77bc077bf3 100644
--- a/sim/bfin/dv-bfin_sic.c
+++ b/sim/bfin/dv-bfin_sic.c
@@ -561,67 +561,73 @@ bfin_sic_561_io_read_buffer (struct hw *me, void *dest, int space,
   { "ivg14", IVG14, 0, output_port, }, \
   { "ivg15", IVG15, 0, output_port, },
 
+/* Give each SIC its own base to make it easier to extract the pin at
+   runtime.  The pin is used as its bit position in the SIC MMRs.  */
+#define ENC(sic, pin) (((sic) << 8) + (pin))
+#define DEC_PIN(pin) ((pin) % 0x100)
+#define DEC_SIC(pin) ((pin) >> 8)
+
 static const struct hw_port_descriptor bfin_sic_50x_ports[] =
 {
   BFIN_SIC_TO_CEC_PORTS
   /* SIC0 */
-  { "pll",            0, 0, input_port, },
-  { "dma_stat",       1, 0, input_port, },
-  { "ppi@0",          2, 0, input_port, },
-  { "sport@0_stat",   3, 0, input_port, },
-  { "sport@1_stat",   4, 0, input_port, },
-  { "uart2@0_stat",   5, 0, input_port, },
-  { "uart2@1_stat",   6, 0, input_port, },
-  { "spi@0",          7, 0, input_port, },
-  { "spi@1",          8, 0, input_port, },
-  { "can_stat",       9, 0, input_port, },
-  { "rsi_int0",      10, 0, input_port, },
-/*{ "reserved",      11, 0, input_port, },*/
-  { "counter@0",     12, 0, input_port, },
-  { "counter@1",     13, 0, input_port, },
-  { "dma@0",         14, 0, input_port, },
-  { "dma@1",         15, 0, input_port, },
-  { "dma@2",         16, 0, input_port, },
-  { "dma@3",         17, 0, input_port, },
-  { "dma@4",         18, 0, input_port, },
-  { "dma@5",         19, 0, input_port, },
-  { "dma@6",         20, 0, input_port, },
-  { "dma@7",         21, 0, input_port, },
-  { "dma@8",         22, 0, input_port, },
-  { "dma@9",         23, 0, input_port, },
-  { "dma@10",        24, 0, input_port, },
-  { "dma@11",        25, 0, input_port, },
-  { "can_rx",        26, 0, input_port, },
-  { "can_tx",        27, 0, input_port, },
-  { "twi@0",         28, 0, input_port, },
-  { "portf_irq_a",   29, 0, input_port, },
-  { "portf_irq_b",   30, 0, input_port, },
-/*{ "reserved",      31, 0, input_port, },*/
+  { "pll",             ENC(0,  0), 0, input_port, },
+  { "dma_stat",        ENC(0,  1), 0, input_port, },
+  { "ppi@0",           ENC(0,  2), 0, input_port, },
+  { "sport@0_stat",    ENC(0,  3), 0, input_port, },
+  { "sport@1_stat",    ENC(0,  4), 0, input_port, },
+  { "uart2@0_stat",    ENC(0,  5), 0, input_port, },
+  { "uart2@1_stat",    ENC(0,  6), 0, input_port, },
+  { "spi@0",           ENC(0,  7), 0, input_port, },
+  { "spi@1",           ENC(0,  8), 0, input_port, },
+  { "can_stat",        ENC(0,  9), 0, input_port, },
+  { "rsi_int0",        ENC(0, 10), 0, input_port, },
+/*{ "reserved",        ENC(0, 11), 0, input_port, },*/
+  { "counter@0",       ENC(0, 12), 0, input_port, },
+  { "counter@1",       ENC(0, 13), 0, input_port, },
+  { "dma@0",           ENC(0, 14), 0, input_port, },
+  { "dma@1",           ENC(0, 15), 0, input_port, },
+  { "dma@2",           ENC(0, 16), 0, input_port, },
+  { "dma@3",           ENC(0, 17), 0, input_port, },
+  { "dma@4",           ENC(0, 18), 0, input_port, },
+  { "dma@5",           ENC(0, 19), 0, input_port, },
+  { "dma@6",           ENC(0, 20), 0, input_port, },
+  { "dma@7",           ENC(0, 21), 0, input_port, },
+  { "dma@8",           ENC(0, 22), 0, input_port, },
+  { "dma@9",           ENC(0, 23), 0, input_port, },
+  { "dma@10",          ENC(0, 24), 0, input_port, },
+  { "dma@11",          ENC(0, 25), 0, input_port, },
+  { "can_rx",          ENC(0, 26), 0, input_port, },
+  { "can_tx",          ENC(0, 27), 0, input_port, },
+  { "twi@0",           ENC(0, 28), 0, input_port, },
+  { "portf_irq_a",     ENC(0, 29), 0, input_port, },
+  { "portf_irq_b",     ENC(0, 30), 0, input_port, },
+/*{ "reserved",        ENC(0, 31), 0, input_port, },*/
   /* SIC1 */
-  { "gptimer@0",    100, 0, input_port, },
-  { "gptimer@1",    101, 0, input_port, },
-  { "gptimer@2",    102, 0, input_port, },
-  { "gptimer@3",    103, 0, input_port, },
-  { "gptimer@4",    104, 0, input_port, },
-  { "gptimer@5",    105, 0, input_port, },
-  { "gptimer@6",    106, 0, input_port, },
-  { "gptimer@7",    107, 0, input_port, },
-  { "portg_irq_a",  108, 0, input_port, },
-  { "portg_irq_b",  109, 0, input_port, },
-  { "mdma@0",       110, 0, input_port, },
-  { "mdma@1",       111, 0, input_port, },
-  { "wdog",         112, 0, input_port, },
-  { "porth_irq_a",  113, 0, input_port, },
-  { "porth_irq_b",  114, 0, input_port, },
-  { "acm_stat",     115, 0, input_port, },
-  { "acm_int",      116, 0, input_port, },
-/*{ "reserved",     117, 0, input_port, },*/
-/*{ "reserved",     118, 0, input_port, },*/
-  { "pwm@0_trip",   119, 0, input_port, },
-  { "pwm@0_sync",   120, 0, input_port, },
-  { "pwm@1_trip",   121, 0, input_port, },
-  { "pwm@1_sync",   122, 0, input_port, },
-  { "rsi_int1",     123, 0, input_port, },
+  { "gptimer@0",       ENC(1,  0), 0, input_port, },
+  { "gptimer@1",       ENC(1,  1), 0, input_port, },
+  { "gptimer@2",       ENC(1,  2), 0, input_port, },
+  { "gptimer@3",       ENC(1,  3), 0, input_port, },
+  { "gptimer@4",       ENC(1,  4), 0, input_port, },
+  { "gptimer@5",       ENC(1,  5), 0, input_port, },
+  { "gptimer@6",       ENC(1,  6), 0, input_port, },
+  { "gptimer@7",       ENC(1,  7), 0, input_port, },
+  { "portg_irq_a",     ENC(1,  8), 0, input_port, },
+  { "portg_irq_b",     ENC(1,  9), 0, input_port, },
+  { "mdma@0",          ENC(1, 10), 0, input_port, },
+  { "mdma@1",          ENC(1, 11), 0, input_port, },
+  { "wdog",            ENC(1, 12), 0, input_port, },
+  { "porth_irq_a",     ENC(1, 13), 0, input_port, },
+  { "porth_irq_b",     ENC(1, 14), 0, input_port, },
+  { "acm_stat",        ENC(1, 15), 0, input_port, },
+  { "acm_int",         ENC(1, 16), 0, input_port, },
+/*{ "reserved",        ENC(1, 17), 0, input_port, },*/
+/*{ "reserved",        ENC(1, 18), 0, input_port, },*/
+  { "pwm@0_trip",      ENC(1, 19), 0, input_port, },
+  { "pwm@0_sync",      ENC(1, 20), 0, input_port, },
+  { "pwm@1_trip",      ENC(1, 21), 0, input_port, },
+  { "pwm@1_sync",      ENC(1, 22), 0, input_port, },
+  { "rsi_int1",        ENC(1, 23), 0, input_port, },
   { NULL, 0, 0, 0, },
 };
 
@@ -629,63 +635,63 @@ static const struct hw_port_descriptor bfin_sic_51x_ports[] =
 {
   BFIN_SIC_TO_CEC_PORTS
   /* SIC0 */
-  { "pll",            0, 0, input_port, },
-  { "dma_stat",       1, 0, input_port, },
-  { "dmar0_block",    2, 0, input_port, },
-  { "dmar1_block",    3, 0, input_port, },
-  { "dmar0_over",     4, 0, input_port, },
-  { "dmar1_over",     5, 0, input_port, },
-  { "ppi@0",          6, 0, input_port, },
-  { "emac_stat",      7, 0, input_port, },
-  { "sport@0_stat",   8, 0, input_port, },
-  { "sport@1_stat",   9, 0, input_port, },
-  { "ptp_err",       10, 0, input_port, },
-/*{ "reserved",      11, 0, input_port, },*/
-  { "uart@0_stat",   12, 0, input_port, },
-  { "uart@1_stat",   13, 0, input_port, },
-  { "rtc",           14, 0, input_port, },
-  { "dma@0",         15, 0, input_port, },
-  { "dma@3",         16, 0, input_port, },
-  { "dma@4",         17, 0, input_port, },
-  { "dma@5",         18, 0, input_port, },
-  { "dma@6",         19, 0, input_port, },
-  { "twi@0",         20, 0, input_port, },
-  { "dma@7",         21, 0, input_port, },
-  { "dma@8",         22, 0, input_port, },
-  { "dma@9",         23, 0, input_port, },
-  { "dma@10",        24, 0, input_port, },
-  { "dma@11",        25, 0, input_port, },
-  { "otp",           26, 0, input_port, },
-  { "counter",       27, 0, input_port, },
-  { "dma@1",         28, 0, input_port, },
-  { "porth_irq_a",   29, 0, input_port, },
-  { "dma@2",         30, 0, input_port, },
-  { "porth_irq_b",   31, 0, input_port, },
+  { "pll",             ENC(0,  0), 0, input_port, },
+  { "dma_stat",        ENC(0,  1), 0, input_port, },
+  { "dmar0_block",     ENC(0,  2), 0, input_port, },
+  { "dmar1_block",     ENC(0,  3), 0, input_port, },
+  { "dmar0_over",      ENC(0,  4), 0, input_port, },
+  { "dmar1_over",      ENC(0,  5), 0, input_port, },
+  { "ppi@0",           ENC(0,  6), 0, input_port, },
+  { "emac_stat",       ENC(0,  7), 0, input_port, },
+  { "sport@0_stat",    ENC(0,  8), 0, input_port, },
+  { "sport@1_stat",    ENC(0,  9), 0, input_port, },
+  { "ptp_err",         ENC(0, 10), 0, input_port, },
+/*{ "reserved",        ENC(0, 11), 0, input_port, },*/
+  { "uart@0_stat",     ENC(0, 12), 0, input_port, },
+  { "uart@1_stat",     ENC(0, 13), 0, input_port, },
+  { "rtc",             ENC(0, 14), 0, input_port, },
+  { "dma@0",           ENC(0, 15), 0, input_port, },
+  { "dma@3",           ENC(0, 16), 0, input_port, },
+  { "dma@4",           ENC(0, 17), 0, input_port, },
+  { "dma@5",           ENC(0, 18), 0, input_port, },
+  { "dma@6",           ENC(0, 19), 0, input_port, },
+  { "twi@0",           ENC(0, 20), 0, input_port, },
+  { "dma@7",           ENC(0, 21), 0, input_port, },
+  { "dma@8",           ENC(0, 22), 0, input_port, },
+  { "dma@9",           ENC(0, 23), 0, input_port, },
+  { "dma@10",          ENC(0, 24), 0, input_port, },
+  { "dma@11",          ENC(0, 25), 0, input_port, },
+  { "otp",             ENC(0, 26), 0, input_port, },
+  { "counter",         ENC(0, 27), 0, input_port, },
+  { "dma@1",           ENC(0, 28), 0, input_port, },
+  { "porth_irq_a",     ENC(0, 29), 0, input_port, },
+  { "dma@2",           ENC(0, 30), 0, input_port, },
+  { "porth_irq_b",     ENC(0, 31), 0, input_port, },
   /* SIC1 */
-  { "gptimer@0",    100, 0, input_port, },
-  { "gptimer@1",    101, 0, input_port, },
-  { "gptimer@2",    102, 0, input_port, },
-  { "gptimer@3",    103, 0, input_port, },
-  { "gptimer@4",    104, 0, input_port, },
-  { "gptimer@5",    105, 0, input_port, },
-  { "gptimer@6",    106, 0, input_port, },
-  { "gptimer@7",    107, 0, input_port, },
-  { "portg_irq_a",  108, 0, input_port, },
-  { "portg_irq_b",  109, 0, input_port, },
-  { "mdma@0",       110, 0, input_port, },
-  { "mdma@1",       111, 0, input_port, },
-  { "wdog",         112, 0, input_port, },
-  { "portf_irq_a",  113, 0, input_port, },
-  { "portf_irq_b",  114, 0, input_port, },
-  { "spi@0",        115, 0, input_port, },
-  { "spi@1",        116, 0, input_port, },
-/*{ "reserved",     117, 0, input_port, },*/
-/*{ "reserved",     118, 0, input_port, },*/
-  { "rsi_int0",     119, 0, input_port, },
-  { "rsi_int1",     120, 0, input_port, },
-  { "pwm_trip",     121, 0, input_port, },
-  { "pwm_sync",     122, 0, input_port, },
-  { "ptp_stat",     123, 0, input_port, },
+  { "gptimer@0",       ENC(1,  0), 0, input_port, },
+  { "gptimer@1",       ENC(1,  1), 0, input_port, },
+  { "gptimer@2",       ENC(1,  2), 0, input_port, },
+  { "gptimer@3",       ENC(1,  3), 0, input_port, },
+  { "gptimer@4",       ENC(1,  4), 0, input_port, },
+  { "gptimer@5",       ENC(1,  5), 0, input_port, },
+  { "gptimer@6",       ENC(1,  6), 0, input_port, },
+  { "gptimer@7",       ENC(1,  7), 0, input_port, },
+  { "portg_irq_a",     ENC(1,  8), 0, input_port, },
+  { "portg_irq_b",     ENC(1,  9), 0, input_port, },
+  { "mdma@0",          ENC(1, 10), 0, input_port, },
+  { "mdma@1",          ENC(1, 11), 0, input_port, },
+  { "wdog",            ENC(1, 12), 0, input_port, },
+  { "portf_irq_a",     ENC(1, 13), 0, input_port, },
+  { "portf_irq_b",     ENC(1, 14), 0, input_port, },
+  { "spi@0",           ENC(1, 15), 0, input_port, },
+  { "spi@1",           ENC(1, 16), 0, input_port, },
+/*{ "reserved",        ENC(1, 17), 0, input_port, },*/
+/*{ "reserved",        ENC(1, 18), 0, input_port, },*/
+  { "rsi_int0",        ENC(1, 19), 0, input_port, },
+  { "rsi_int1",        ENC(1, 20), 0, input_port, },
+  { "pwm_trip",        ENC(1, 21), 0, input_port, },
+  { "pwm_sync",        ENC(1, 22), 0, input_port, },
+  { "ptp_stat",        ENC(1, 23), 0, input_port, },
   { NULL, 0, 0, 0, },
 };
 
@@ -693,61 +699,61 @@ static const struct hw_port_descriptor bfin_sic_52x_ports[] =
 {
   BFIN_SIC_TO_CEC_PORTS
   /* SIC0 */
-  { "pll",            0, 0, input_port, },
-  { "dma_stat",       1, 0, input_port, },
-  { "dmar0_block",    2, 0, input_port, },
-  { "dmar1_block",    3, 0, input_port, },
-  { "dmar0_over",     4, 0, input_port, },
-  { "dmar1_over",     5, 0, input_port, },
-  { "ppi@0",          6, 0, input_port, },
-  { "emac_stat",      7, 0, input_port, },
-  { "sport@0_stat",   8, 0, input_port, },
-  { "sport@1_stat",   9, 0, input_port, },
-/*{ "reserved",      10, 0, input_port, },*/
-/*{ "reserved",      11, 0, input_port, },*/
-  { "uart@0_stat",   12, 0, input_port, },
-  { "uart@1_stat",   13, 0, input_port, },
-  { "rtc",           14, 0, input_port, },
-  { "dma@0",         15, 0, input_port, },
-  { "dma@3",         16, 0, input_port, },
-  { "dma@4",         17, 0, input_port, },
-  { "dma@5",         18, 0, input_port, },
-  { "dma@6",         19, 0, input_port, },
-  { "twi@0",         20, 0, input_port, },
-  { "dma@7",         21, 0, input_port, },
-  { "dma@8",         22, 0, input_port, },
-  { "dma@9",         23, 0, input_port, },
-  { "dma@10",        24, 0, input_port, },
-  { "dma@11",        25, 0, input_port, },
-  { "otp",           26, 0, input_port, },
-  { "counter",       27, 0, input_port, },
-  { "dma@1",         28, 0, input_port, },
-  { "porth_irq_a",   29, 0, input_port, },
-  { "dma@2",         30, 0, input_port, },
-  { "porth_irq_b",   31, 0, input_port, },
+  { "pll",             ENC(0,  0), 0, input_port, },
+  { "dma_stat",        ENC(0,  1), 0, input_port, },
+  { "dmar0_block",     ENC(0,  2), 0, input_port, },
+  { "dmar1_block",     ENC(0,  3), 0, input_port, },
+  { "dmar0_over",      ENC(0,  4), 0, input_port, },
+  { "dmar1_over",      ENC(0,  5), 0, input_port, },
+  { "ppi@0",           ENC(0,  6), 0, input_port, },
+  { "emac_stat",       ENC(0,  7), 0, input_port, },
+  { "sport@0_stat",    ENC(0,  8), 0, input_port, },
+  { "sport@1_stat",    ENC(0,  9), 0, input_port, },
+/*{ "reserved",        ENC(0, 10), 0, input_port, },*/
+/*{ "reserved",        ENC(0, 11), 0, input_port, },*/
+  { "uart@0_stat",     ENC(0, 12), 0, input_port, },
+  { "uart@1_stat",     ENC(0, 13), 0, input_port, },
+  { "rtc",             ENC(0, 14), 0, input_port, },
+  { "dma@0",           ENC(0, 15), 0, input_port, },
+  { "dma@3",           ENC(0, 16), 0, input_port, },
+  { "dma@4",           ENC(0, 17), 0, input_port, },
+  { "dma@5",           ENC(0, 18), 0, input_port, },
+  { "dma@6",           ENC(0, 19), 0, input_port, },
+  { "twi@0",           ENC(0, 20), 0, input_port, },
+  { "dma@7",           ENC(0, 21), 0, input_port, },
+  { "dma@8",           ENC(0, 22), 0, input_port, },
+  { "dma@9",           ENC(0, 23), 0, input_port, },
+  { "dma@10",          ENC(0, 24), 0, input_port, },
+  { "dma@11",          ENC(0, 25), 0, input_port, },
+  { "otp",             ENC(0, 26), 0, input_port, },
+  { "counter",         ENC(0, 27), 0, input_port, },
+  { "dma@1",           ENC(0, 28), 0, input_port, },
+  { "porth_irq_a",     ENC(0, 29), 0, input_port, },
+  { "dma@2",           ENC(0, 30), 0, input_port, },
+  { "porth_irq_b",     ENC(0, 31), 0, input_port, },
   /* SIC1 */
-  { "gptimer@0",    100, 0, input_port, },
-  { "gptimer@1",    101, 0, input_port, },
-  { "gptimer@2",    102, 0, input_port, },
-  { "gptimer@3",    103, 0, input_port, },
-  { "gptimer@4",    104, 0, input_port, },
-  { "gptimer@5",    105, 0, input_port, },
-  { "gptimer@6",    106, 0, input_port, },
-  { "gptimer@7",    107, 0, input_port, },
-  { "portg_irq_a",  108, 0, input_port, },
-  { "portg_irq_b",  109, 0, input_port, },
-  { "mdma@0",       110, 0, input_port, },
-  { "mdma@1",       111, 0, input_port, },
-  { "wdog",         112, 0, input_port, },
-  { "portf_irq_a",  113, 0, input_port, },
-  { "portf_irq_b",  114, 0, input_port, },
-  { "spi@0",        115, 0, input_port, },
-  { "nfc_stat",     116, 0, input_port, },
-  { "hostdp_stat",  117, 0, input_port, },
-  { "hostdp_done",  118, 0, input_port, },
-  { "usb_int0",     120, 0, input_port, },
-  { "usb_int1",     121, 0, input_port, },
-  { "usb_int2",     122, 0, input_port, },
+  { "gptimer@0",       ENC(1,  0), 0, input_port, },
+  { "gptimer@1",       ENC(1,  1), 0, input_port, },
+  { "gptimer@2",       ENC(1,  2), 0, input_port, },
+  { "gptimer@3",       ENC(1,  3), 0, input_port, },
+  { "gptimer@4",       ENC(1,  4), 0, input_port, },
+  { "gptimer@5",       ENC(1,  5), 0, input_port, },
+  { "gptimer@6",       ENC(1,  6), 0, input_port, },
+  { "gptimer@7",       ENC(1,  7), 0, input_port, },
+  { "portg_irq_a",     ENC(1,  8), 0, input_port, },
+  { "portg_irq_b",     ENC(1,  9), 0, input_port, },
+  { "mdma@0",          ENC(1, 10), 0, input_port, },
+  { "mdma@1",          ENC(1, 11), 0, input_port, },
+  { "wdog",            ENC(1, 12), 0, input_port, },
+  { "portf_irq_a",     ENC(1, 13), 0, input_port, },
+  { "portf_irq_b",     ENC(1, 14), 0, input_port, },
+  { "spi@0",           ENC(1, 15), 0, input_port, },
+  { "nfc_stat",        ENC(1, 16), 0, input_port, },
+  { "hostdp_stat",     ENC(1, 17), 0, input_port, },
+  { "hostdp_done",     ENC(1, 18), 0, input_port, },
+  { "usb_int0",        ENC(1, 20), 0, input_port, },
+  { "usb_int1",        ENC(1, 21), 0, input_port, },
+  { "usb_int2",        ENC(1, 22), 0, input_port, },
   { NULL, 0, 0, 0, },
 };
 
@@ -756,8 +762,8 @@ bfin_sic_52x_port_event (struct hw *me, int my_port, struct hw *source,
 			 int source_port, int level)
 {
   struct bfin_sic *sic = hw_data (me);
-  bu32 idx = my_port / 100;
-  bu32 bit = (1 << (my_port & 0x1f));
+  bu32 idx = DEC_SIC (my_port);
+  bu32 bit = 1 << DEC_PIN (my_port);
 
   /* SIC only exists to forward interrupts from the system to the CEC.  */
   switch (idx)
@@ -779,101 +785,86 @@ bfin_sic_52x_port_event (struct hw *me, int my_port, struct hw *source,
 static const struct hw_port_descriptor bfin_sic_533_ports[] =
 {
   BFIN_SIC_TO_CEC_PORTS
-  { "pll",            0, 0, input_port, },
-  { "dma_stat",       1, 0, input_port, },
-  { "ppi@0",          2, 0, input_port, },
-  { "sport@0_stat",   3, 0, input_port, },
-  { "sport@1_stat",   4, 0, input_port, },
-  { "spi@0",          5, 0, input_port, },
-  { "uart@0_stat",    6, 0, input_port, },
-  { "rtc",            7, 0, input_port, },
-  { "dma@0",          8, 0, input_port, },
-  { "dma@1",          9, 0, input_port, },
-  { "dma@2",         10, 0, input_port, },
-  { "dma@3",         11, 0, input_port, },
-  { "dma@4",         12, 0, input_port, },
-  { "dma@5",         13, 0, input_port, },
-  { "dma@6",         14, 0, input_port, },
-  { "dma@7",         15, 0, input_port, },
-  { "gptimer@0",     16, 0, input_port, },
-  { "gptimer@1",     17, 0, input_port, },
-  { "gptimer@2",     18, 0, input_port, },
-  { "portf_irq_a",   19, 0, input_port, },
-  { "portf_irq_b",   20, 0, input_port, },
-  { "mdma@0",        21, 0, input_port, },
-  { "mdma@1",        22, 0, input_port, },
-  { "wdog",          23, 0, input_port, },
+  { "pll",             ENC(0,  0), 0, input_port, },
+  { "dma_stat",        ENC(0,  1), 0, input_port, },
+  { "ppi@0",           ENC(0,  2), 0, input_port, },
+  { "sport@0_stat",    ENC(0,  3), 0, input_port, },
+  { "sport@1_stat",    ENC(0,  4), 0, input_port, },
+  { "spi@0",           ENC(0,  5), 0, input_port, },
+  { "uart@0_stat",     ENC(0,  6), 0, input_port, },
+  { "rtc",             ENC(0,  7), 0, input_port, },
+  { "dma@0",           ENC(0,  8), 0, input_port, },
+  { "dma@1",           ENC(0,  9), 0, input_port, },
+  { "dma@2",           ENC(0, 10), 0, input_port, },
+  { "dma@3",           ENC(0, 11), 0, input_port, },
+  { "dma@4",           ENC(0, 12), 0, input_port, },
+  { "dma@5",           ENC(0, 13), 0, input_port, },
+  { "dma@6",           ENC(0, 14), 0, input_port, },
+  { "dma@7",           ENC(0, 15), 0, input_port, },
+  { "gptimer@0",       ENC(0, 16), 0, input_port, },
+  { "gptimer@1",       ENC(0, 17), 0, input_port, },
+  { "gptimer@2",       ENC(0, 18), 0, input_port, },
+  { "portf_irq_a",     ENC(0, 19), 0, input_port, },
+  { "portf_irq_b",     ENC(0, 20), 0, input_port, },
+  { "mdma@0",          ENC(0, 21), 0, input_port, },
+  { "mdma@1",          ENC(0, 22), 0, input_port, },
+  { "wdog",            ENC(0, 23), 0, input_port, },
   { NULL, 0, 0, 0, },
 };
 
-static void
-bfin_sic_533_port_event (struct hw *me, int my_port, struct hw *source,
-			 int source_port, int level)
-{
-  struct bfin_sic *sic = hw_data (me);
-  bu32 bit = (1 << my_port);
-
-  /* SIC only exists to forward interrupts from the system to the CEC.  */
-  sic->bf537.isr |= bit;
-
-  /* XXX: Handle SIC wakeup source ?
-  if (sic->bf537.iwr & bit)
-    What to do ?;
-   */
-
-  bfin_sic_537_forward_interrupts (me, sic);
-}
-
+/* The encoding here is uglier due to multiple sources being muxed into
+   the same interrupt line.  So give each pin an arbitrary "SIC" so that
+   the resulting id is unique across all ports.  */
 static const struct hw_port_descriptor bfin_sic_537_ports[] =
 {
   BFIN_SIC_TO_CEC_PORTS
-  { "pll",            0, 0, input_port, },
-  { "dma_stat",      10, 0, input_port, },
-  { "dmar0_block",   11, 0, input_port, },
-  { "dmar1_block",   12, 0, input_port, },
-  { "dmar0_over",    13, 0, input_port, },
-  { "dmar1_over",    14, 0, input_port, },
-  { "can_stat",      20, 0, input_port, },
-  { "emac_stat",     21, 0, input_port, },
-  { "sport@0_stat",  22, 0, input_port, },
-  { "sport@1_stat",  23, 0, input_port, },
-  { "ppi@0",         24, 0, input_port, },
-  { "spi@0",         25, 0, input_port, },
-  { "uart@0_stat",   26, 0, input_port, },
-  { "uart@1_stat",   27, 0, input_port, },
-  { "rtc",           30, 0, input_port, },
-  { "dma@0",         40, 0, input_port, },
-  { "dma@3",         50, 0, input_port, },
-  { "dma@4",         60, 0, input_port, },
-  { "dma@5",         70, 0, input_port, },
-  { "dma@6",         80, 0, input_port, },
-  { "twi@0",         90, 0, input_port, },
-  { "dma@7",        100, 0, input_port, },
-  { "dma@8",        110, 0, input_port, },
-  { "dma@9",        120, 0, input_port, },
-  { "dma@10",       130, 0, input_port, },
-  { "dma@11",       140, 0, input_port, },
-  { "can_rx",       150, 0, input_port, },
-  { "can_tx",       160, 0, input_port, },
-  { "dma@1",        170, 0, input_port, },
-  { "porth_irq_a",  171, 0, input_port, },
-  { "dma@2",        180, 0, input_port, },
-  { "porth_irq_b",  181, 0, input_port, },
-  { "gptimer@0",    190, 0, input_port, },
-  { "gptimer@1",    200, 0, input_port, },
-  { "gptimer@2",    210, 0, input_port, },
-  { "gptimer@3",    220, 0, input_port, },
-  { "gptimer@4",    230, 0, input_port, },
-  { "gptimer@5",    240, 0, input_port, },
-  { "gptimer@6",    250, 0, input_port, },
-  { "gptimer@7",    260, 0, input_port, },
-  { "portf_irq_a",  270, 0, input_port, },
-  { "portg_irq_a",  271, 0, input_port, },
-  { "portg_irq_b",  280, 0, input_port, },
-  { "mdma@0",       290, 0, input_port, },
-  { "mdma@1",       300, 0, input_port, },
-  { "wdog",         310, 0, input_port, },
-  { "portf_irq_b",  311, 0, input_port, },
+  { "pll",             ENC(0,  0), 0, input_port, },
+  { "dma_stat",        ENC(0,  1), 0, input_port, },
+  { "dmar0_block",     ENC(1,  1), 0, input_port, },
+  { "dmar1_block",     ENC(2,  1), 0, input_port, },
+  { "dmar0_over",      ENC(3,  1), 0, input_port, },
+  { "dmar1_over",      ENC(4,  1), 0, input_port, },
+  { "can_stat",        ENC(0,  2), 0, input_port, },
+  { "emac_stat",       ENC(1,  2), 0, input_port, },
+  { "sport@0_stat",    ENC(2,  2), 0, input_port, },
+  { "sport@1_stat",    ENC(3,  2), 0, input_port, },
+  { "ppi@0",           ENC(4,  2), 0, input_port, },
+  { "spi@0",           ENC(5,  2), 0, input_port, },
+  { "uart@0_stat",     ENC(6,  2), 0, input_port, },
+  { "uart@1_stat",     ENC(7,  2), 0, input_port, },
+  { "rtc",             ENC(0,  3), 0, input_port, },
+  { "dma@0",           ENC(0,  4), 0, input_port, },
+  { "dma@3",           ENC(0,  5), 0, input_port, },
+  { "dma@4",           ENC(0,  6), 0, input_port, },
+  { "dma@5",           ENC(0,  7), 0, input_port, },
+  { "dma@6",           ENC(0,  8), 0, input_port, },
+  { "twi@0",           ENC(0,  9), 0, input_port, },
+  { "dma@7",           ENC(0, 10), 0, input_port, },
+  { "dma@8",           ENC(0, 11), 0, input_port, },
+  { "dma@9",           ENC(0, 12), 0, input_port, },
+  { "dma@10",          ENC(0, 13), 0, input_port, },
+  { "dma@11",          ENC(0, 14), 0, input_port, },
+  { "can_rx",          ENC(0, 15), 0, input_port, },
+  { "can_tx",          ENC(0, 16), 0, input_port, },
+  { "dma@1",           ENC(0, 17), 0, input_port, },
+  { "porth_irq_a",     ENC(1, 17), 0, input_port, },
+  { "dma@2",           ENC(0, 18), 0, input_port, },
+  { "porth_irq_b",     ENC(1, 18), 0, input_port, },
+  { "gptimer@0",       ENC(0, 19), 0, input_port, },
+  { "gptimer@1",       ENC(0, 20), 0, input_port, },
+  { "gptimer@2",       ENC(0, 21), 0, input_port, },
+  { "gptimer@3",       ENC(0, 22), 0, input_port, },
+  { "gptimer@4",       ENC(0, 23), 0, input_port, },
+  { "gptimer@5",       ENC(0, 24), 0, input_port, },
+  { "gptimer@6",       ENC(0, 25), 0, input_port, },
+  { "gptimer@7",       ENC(0, 26), 0, input_port, },
+  { "portf_irq_a",     ENC(0, 27), 0, input_port, },
+  { "portg_irq_a",     ENC(1, 27), 0, input_port, },
+  { "portg_irq_b",     ENC(0, 28), 0, input_port, },
+  { "mdma@0",          ENC(0, 29), 0, input_port, },
+  { "mdma@1",          ENC(0, 30), 0, input_port, },
+  { "wdog",            ENC(0, 31), 0, input_port, },
+  { "portf_irq_b",     ENC(1, 31), 0, input_port, },
   { NULL, 0, 0, 0, },
 };
 
@@ -882,7 +873,7 @@ bfin_sic_537_port_event (struct hw *me, int my_port, struct hw *source,
 			 int source_port, int level)
 {
   struct bfin_sic *sic = hw_data (me);
-  bu32 bit = (1 << (my_port / 10));
+  bu32 bit = 1 << DEC_PIN (my_port);
 
   /* SIC only exists to forward interrupts from the system to the CEC.  */
   sic->bf537.isr |= bit;
@@ -899,58 +890,58 @@ static const struct hw_port_descriptor bfin_sic_538_ports[] =
 {
   BFIN_SIC_TO_CEC_PORTS
   /* SIC0 */
-  { "pll",            0, 0, input_port, },
-  { "dmac@0_stat",    1, 0, input_port, },
-  { "ppi@0",          2, 0, input_port, },
-  { "sport@0_stat",   3, 0, input_port, },
-  { "sport@1_stat",   4, 0, input_port, },
-  { "spi@0",          5, 0, input_port, },
-  { "uart@0_stat",    6, 0, input_port, },
-  { "rtc",            7, 0, input_port, },
-  { "dma@0",          8, 0, input_port, },
-  { "dma@1",          9, 0, input_port, },
-  { "dma@2",         10, 0, input_port, },
-  { "dma@3",         11, 0, input_port, },
-  { "dma@4",         12, 0, input_port, },
-  { "dma@5",         13, 0, input_port, },
-  { "dma@6",         14, 0, input_port, },
-  { "dma@7",         15, 0, input_port, },
-  { "gptimer@0",     16, 0, input_port, },
-  { "gptimer@1",     17, 0, input_port, },
-  { "gptimer@2",     18, 0, input_port, },
-  { "portf_irq_a",   19, 0, input_port, },
-  { "portf_irq_b",   20, 0, input_port, },
-  { "mdma@0",        21, 0, input_port, },
-  { "mdma@1",        22, 0, input_port, },
-  { "wdog",          23, 0, input_port, },
-  { "dmac@1_stat",   24, 0, input_port, },
-  { "sport@2_stat",  25, 0, input_port, },
-  { "sport@3_stat",  26, 0, input_port, },
-/*{ "reserved",      27, 0, input_port, },*/
-  { "spi@1",         28, 0, input_port, },
-  { "spi@2",         29, 0, input_port, },
-  { "uart@1_stat",   30, 0, input_port, },
-  { "uart@2_stat",   31, 0, input_port, },
+  { "pll",             ENC(0,  0), 0, input_port, },
+  { "dmac@0_stat",     ENC(0,  1), 0, input_port, },
+  { "ppi@0",           ENC(0,  2), 0, input_port, },
+  { "sport@0_stat",    ENC(0,  3), 0, input_port, },
+  { "sport@1_stat",    ENC(0,  4), 0, input_port, },
+  { "spi@0",           ENC(0,  5), 0, input_port, },
+  { "uart@0_stat",     ENC(0,  6), 0, input_port, },
+  { "rtc",             ENC(0,  7), 0, input_port, },
+  { "dma@0",           ENC(0,  8), 0, input_port, },
+  { "dma@1",           ENC(0,  9), 0, input_port, },
+  { "dma@2",           ENC(0, 10), 0, input_port, },
+  { "dma@3",           ENC(0, 11), 0, input_port, },
+  { "dma@4",           ENC(0, 12), 0, input_port, },
+  { "dma@5",           ENC(0, 13), 0, input_port, },
+  { "dma@6",           ENC(0, 14), 0, input_port, },
+  { "dma@7",           ENC(0, 15), 0, input_port, },
+  { "gptimer@0",       ENC(0, 16), 0, input_port, },
+  { "gptimer@1",       ENC(0, 17), 0, input_port, },
+  { "gptimer@2",       ENC(0, 18), 0, input_port, },
+  { "portf_irq_a",     ENC(0, 19), 0, input_port, },
+  { "portf_irq_b",     ENC(0, 20), 0, input_port, },
+  { "mdma@0",          ENC(0, 21), 0, input_port, },
+  { "mdma@1",          ENC(0, 22), 0, input_port, },
+  { "wdog",            ENC(0, 23), 0, input_port, },
+  { "dmac@1_stat",     ENC(0, 24), 0, input_port, },
+  { "sport@2_stat",    ENC(0, 25), 0, input_port, },
+  { "sport@3_stat",    ENC(0, 26), 0, input_port, },
+/*{ "reserved",        ENC(0, 27), 0, input_port, },*/
+  { "spi@1",           ENC(0, 28), 0, input_port, },
+  { "spi@2",           ENC(0, 29), 0, input_port, },
+  { "uart@1_stat",     ENC(0, 30), 0, input_port, },
+  { "uart@2_stat",     ENC(0, 31), 0, input_port, },
   /* SIC1 */
-  { "can_stat",     100, 0, input_port, },
-  { "dma@8",        101, 0, input_port, },
-  { "dma@9",        102, 0, input_port, },
-  { "dma@10",       103, 0, input_port, },
-  { "dma@11",       104, 0, input_port, },
-  { "dma@12",       105, 0, input_port, },
-  { "dma@13",       106, 0, input_port, },
-  { "dma@14",       107, 0, input_port, },
-  { "dma@15",       108, 0, input_port, },
-  { "dma@16",       109, 0, input_port, },
-  { "dma@17",       110, 0, input_port, },
-  { "dma@18",       111, 0, input_port, },
-  { "dma@19",       112, 0, input_port, },
-  { "twi@0",        113, 0, input_port, },
-  { "twi@1",        114, 0, input_port, },
-  { "can_rx",       115, 0, input_port, },
-  { "can_tx",       116, 0, input_port, },
-  { "mdma@2",       117, 0, input_port, },
-  { "mdma@3",       118, 0, input_port, },
+  { "can_stat",        ENC(1,  0), 0, input_port, },
+  { "dma@8",           ENC(1,  1), 0, input_port, },
+  { "dma@9",           ENC(1,  2), 0, input_port, },
+  { "dma@10",          ENC(1,  3), 0, input_port, },
+  { "dma@11",          ENC(1,  4), 0, input_port, },
+  { "dma@12",          ENC(1,  5), 0, input_port, },
+  { "dma@13",          ENC(1,  6), 0, input_port, },
+  { "dma@14",          ENC(1,  7), 0, input_port, },
+  { "dma@15",          ENC(1,  8), 0, input_port, },
+  { "dma@16",          ENC(1,  9), 0, input_port, },
+  { "dma@17",          ENC(1, 10), 0, input_port, },
+  { "dma@18",          ENC(1, 11), 0, input_port, },
+  { "dma@19",          ENC(1, 12), 0, input_port, },
+  { "twi@0",           ENC(1, 13), 0, input_port, },
+  { "twi@1",           ENC(1, 14), 0, input_port, },
+  { "can_rx",          ENC(1, 15), 0, input_port, },
+  { "can_tx",          ENC(1, 16), 0, input_port, },
+  { "mdma@2",          ENC(1, 17), 0, input_port, },
+  { "mdma@3",          ENC(1, 18), 0, input_port, },
   { NULL, 0, 0, 0, },
 };
 
@@ -958,104 +949,104 @@ static const struct hw_port_descriptor bfin_sic_54x_ports[] =
 {
   BFIN_SIC_TO_CEC_PORTS
   /* SIC0 */
-  { "pll",            0, 0, input_port, },
-  { "dmac@0_stat",    1, 0, input_port, },
-  { "eppi@0",         2, 0, input_port, },
-  { "sport@0_stat",   3, 0, input_port, },
-  { "sport@1_stat",   4, 0, input_port, },
-  { "spi@0",          5, 0, input_port, },
-  { "uart2@0_stat",   6, 0, input_port, },
-  { "rtc",            7, 0, input_port, },
-  { "dma@12",         8, 0, input_port, },
-  { "dma@0",          9, 0, input_port, },
-  { "dma@1",         10, 0, input_port, },
-  { "dma@2",         11, 0, input_port, },
-  { "dma@3",         12, 0, input_port, },
-  { "dma@4",         13, 0, input_port, },
-  { "dma@6",         14, 0, input_port, },
-  { "dma@7",         15, 0, input_port, },
-  { "gptimer@8",     16, 0, input_port, },
-  { "gptimer@9",     17, 0, input_port, },
-  { "gptimer@10",    18, 0, input_port, },
-  { "pint@0",        19, 0, input_port, },
-  { "pint@1",        20, 0, input_port, },
-  { "mdma@0",        21, 0, input_port, },
-  { "mdma@1",        22, 0, input_port, },
-  { "wdog",          23, 0, input_port, },
-  { "dmac@1_stat",   24, 0, input_port, },
-  { "sport@2_stat",  25, 0, input_port, },
-  { "sport@3_stat",  26, 0, input_port, },
-  { "mxvr",          27, 0, input_port, },
-  { "spi@1",         28, 0, input_port, },
-  { "spi@2",         29, 0, input_port, },
-  { "uart2@1_stat",  30, 0, input_port, },
-  { "uart2@2_stat",  31, 0, input_port, },
+  { "pll",             ENC(0,  0), 0, input_port, },
+  { "dmac@0_stat",     ENC(0,  1), 0, input_port, },
+  { "eppi@0",          ENC(0,  2), 0, input_port, },
+  { "sport@0_stat",    ENC(0,  3), 0, input_port, },
+  { "sport@1_stat",    ENC(0,  4), 0, input_port, },
+  { "spi@0",           ENC(0,  5), 0, input_port, },
+  { "uart2@0_stat",    ENC(0,  6), 0, input_port, },
+  { "rtc",             ENC(0,  7), 0, input_port, },
+  { "dma@12",          ENC(0,  8), 0, input_port, },
+  { "dma@0",           ENC(0,  9), 0, input_port, },
+  { "dma@1",           ENC(0, 10), 0, input_port, },
+  { "dma@2",           ENC(0, 11), 0, input_port, },
+  { "dma@3",           ENC(0, 12), 0, input_port, },
+  { "dma@4",           ENC(0, 13), 0, input_port, },
+  { "dma@6",           ENC(0, 14), 0, input_port, },
+  { "dma@7",           ENC(0, 15), 0, input_port, },
+  { "gptimer@8",       ENC(0, 16), 0, input_port, },
+  { "gptimer@9",       ENC(0, 17), 0, input_port, },
+  { "gptimer@10",      ENC(0, 18), 0, input_port, },
+  { "pint@0",          ENC(0, 19), 0, input_port, },
+  { "pint@1",          ENC(0, 20), 0, input_port, },
+  { "mdma@0",          ENC(0, 21), 0, input_port, },
+  { "mdma@1",          ENC(0, 22), 0, input_port, },
+  { "wdog",            ENC(0, 23), 0, input_port, },
+  { "dmac@1_stat",     ENC(0, 24), 0, input_port, },
+  { "sport@2_stat",    ENC(0, 25), 0, input_port, },
+  { "sport@3_stat",    ENC(0, 26), 0, input_port, },
+  { "mxvr",            ENC(0, 27), 0, input_port, },
+  { "spi@1",           ENC(0, 28), 0, input_port, },
+  { "spi@2",           ENC(0, 29), 0, input_port, },
+  { "uart2@1_stat",    ENC(0, 30), 0, input_port, },
+  { "uart2@2_stat",    ENC(0, 31), 0, input_port, },
   /* SIC1 */
-  { "can@0_stat",    32, 0, input_port, },
-  { "dma@18",        33, 0, input_port, },
-  { "dma@19",        34, 0, input_port, },
-  { "dma@20",        35, 0, input_port, },
-  { "dma@21",        36, 0, input_port, },
-  { "dma@13",        37, 0, input_port, },
-  { "dma@14",        38, 0, input_port, },
-  { "dma@5",         39, 0, input_port, },
-  { "dma@23",        40, 0, input_port, },
-  { "dma@8",         41, 0, input_port, },
-  { "dma@9",         42, 0, input_port, },
-  { "dma@10",        43, 0, input_port, },
-  { "dma@11",        44, 0, input_port, },
-  { "twi@0",         45, 0, input_port, },
-  { "twi@1",         46, 0, input_port, },
-  { "can@0_rx",      47, 0, input_port, },
-  { "can@0_tx",      48, 0, input_port, },
-  { "mdma@2",        49, 0, input_port, },
-  { "mdma@3",        50, 0, input_port, },
-  { "mxvr_stat",     51, 0, input_port, },
-  { "mxvr_message",  52, 0, input_port, },
-  { "mxvr_packet",   53, 0, input_port, },
-  { "eppi@1",        54, 0, input_port, },
-  { "eppi@2",        55, 0, input_port, },
-  { "uart2@3_stat",  56, 0, input_port, },
-  { "hostdp",        57, 0, input_port, },
-/*{ "reserved",      58, 0, input_port, },*/
-  { "pixc_stat",     59, 0, input_port, },
-  { "nfc",           60, 0, input_port, },
-  { "atapi",         61, 0, input_port, },
-  { "can@1_stat",    62, 0, input_port, },
-  { "dmar",          63, 0, input_port, },
+  { "can@0_stat",      ENC(1,  0), 0, input_port, },
+  { "dma@18",          ENC(1,  1), 0, input_port, },
+  { "dma@19",          ENC(1,  2), 0, input_port, },
+  { "dma@20",          ENC(1,  3), 0, input_port, },
+  { "dma@21",          ENC(1,  4), 0, input_port, },
+  { "dma@13",          ENC(1,  5), 0, input_port, },
+  { "dma@14",          ENC(1,  6), 0, input_port, },
+  { "dma@5",           ENC(1,  7), 0, input_port, },
+  { "dma@23",          ENC(1,  8), 0, input_port, },
+  { "dma@8",           ENC(1,  9), 0, input_port, },
+  { "dma@9",           ENC(1, 10), 0, input_port, },
+  { "dma@10",          ENC(1, 11), 0, input_port, },
+  { "dma@11",          ENC(1, 12), 0, input_port, },
+  { "twi@0",           ENC(1, 13), 0, input_port, },
+  { "twi@1",           ENC(1, 14), 0, input_port, },
+  { "can@0_rx",        ENC(1, 15), 0, input_port, },
+  { "can@0_tx",        ENC(1, 16), 0, input_port, },
+  { "mdma@2",          ENC(1, 17), 0, input_port, },
+  { "mdma@3",          ENC(1, 18), 0, input_port, },
+  { "mxvr_stat",       ENC(1, 19), 0, input_port, },
+  { "mxvr_message",    ENC(1, 20), 0, input_port, },
+  { "mxvr_packet",     ENC(1, 21), 0, input_port, },
+  { "eppi@1",          ENC(1, 22), 0, input_port, },
+  { "eppi@2",          ENC(1, 23), 0, input_port, },
+  { "uart2@3_stat",    ENC(1, 24), 0, input_port, },
+  { "hostdp",          ENC(1, 25), 0, input_port, },
+/*{ "reserved",        ENC(1, 26), 0, input_port, },*/
+  { "pixc_stat",       ENC(1, 27), 0, input_port, },
+  { "nfc",             ENC(1, 28), 0, input_port, },
+  { "atapi",           ENC(1, 29), 0, input_port, },
+  { "can@1_stat",      ENC(1, 30), 0, input_port, },
+  { "dmar",            ENC(1, 31), 0, input_port, },
   /* SIC2 */
-  { "dma@15",        64, 0, input_port, },
-  { "dma@16",        65, 0, input_port, },
-  { "dma@17",        66, 0, input_port, },
-  { "dma@22",        67, 0, input_port, },
-  { "counter",       68, 0, input_port, },
-  { "key",           69, 0, input_port, },
-  { "can@1_rx",      70, 0, input_port, },
-  { "can@1_tx",      71, 0, input_port, },
-  { "sdh_mask0",     72, 0, input_port, },
-  { "sdh_mask1",     73, 0, input_port, },
-/*{ "reserved",      74, 0, input_port, },*/
-  { "usb_int0",      75, 0, input_port, },
-  { "usb_int1",      76, 0, input_port, },
-  { "usb_int2",      77, 0, input_port, },
-  { "usb_dma",       78, 0, input_port, },
-  { "otpsec",        79, 0, input_port, },
-/*{ "reserved",      80, 0, input_port, },*/
-/*{ "reserved",      81, 0, input_port, },*/
-/*{ "reserved",      82, 0, input_port, },*/
-/*{ "reserved",      83, 0, input_port, },*/
-/*{ "reserved",      84, 0, input_port, },*/
-/*{ "reserved",      85, 0, input_port, },*/
-  { "gptimer@0",     86, 0, input_port, },
-  { "gptimer@1",     87, 0, input_port, },
-  { "gptimer@2",     88, 0, input_port, },
-  { "gptimer@3",     89, 0, input_port, },
-  { "gptimer@4",     90, 0, input_port, },
-  { "gptimer@5",     91, 0, input_port, },
-  { "gptimer@6",     92, 0, input_port, },
-  { "gptimer@7",     93, 0, input_port, },
-  { "pint2",         94, 0, input_port, },
-  { "pint3",         95, 0, input_port, },
+  { "dma@15",          ENC(2,  0), 0, input_port, },
+  { "dma@16",          ENC(2,  1), 0, input_port, },
+  { "dma@17",          ENC(2,  2), 0, input_port, },
+  { "dma@22",          ENC(2,  3), 0, input_port, },
+  { "counter",         ENC(2,  4), 0, input_port, },
+  { "key",             ENC(2,  5), 0, input_port, },
+  { "can@1_rx",        ENC(2,  6), 0, input_port, },
+  { "can@1_tx",        ENC(2,  7), 0, input_port, },
+  { "sdh_mask0",       ENC(2,  8), 0, input_port, },
+  { "sdh_mask1",       ENC(2,  9), 0, input_port, },
+/*{ "reserved",        ENC(2, 10), 0, input_port, },*/
+  { "usb_int0",        ENC(2, 11), 0, input_port, },
+  { "usb_int1",        ENC(2, 12), 0, input_port, },
+  { "usb_int2",        ENC(2, 13), 0, input_port, },
+  { "usb_dma",         ENC(2, 14), 0, input_port, },
+  { "otpsec",          ENC(2, 15), 0, input_port, },
+/*{ "reserved",        ENC(2, 16), 0, input_port, },*/
+/*{ "reserved",        ENC(2, 17), 0, input_port, },*/
+/*{ "reserved",        ENC(2, 18), 0, input_port, },*/
+/*{ "reserved",        ENC(2, 19), 0, input_port, },*/
+/*{ "reserved",        ENC(2, 20), 0, input_port, },*/
+/*{ "reserved",        ENC(2, 21), 0, input_port, },*/
+  { "gptimer@0",       ENC(2, 22), 0, input_port, },
+  { "gptimer@1",       ENC(2, 23), 0, input_port, },
+  { "gptimer@2",       ENC(2, 24), 0, input_port, },
+  { "gptimer@3",       ENC(2, 25), 0, input_port, },
+  { "gptimer@4",       ENC(2, 26), 0, input_port, },
+  { "gptimer@5",       ENC(2, 27), 0, input_port, },
+  { "gptimer@6",       ENC(2, 28), 0, input_port, },
+  { "gptimer@7",       ENC(2, 29), 0, input_port, },
+  { "pint2",           ENC(2, 30), 0, input_port, },
+  { "pint3",           ENC(2, 31), 0, input_port, },
   { NULL, 0, 0, 0, },
 };
 
@@ -1064,8 +1055,8 @@ bfin_sic_54x_port_event (struct hw *me, int my_port, struct hw *source,
 			 int source_port, int level)
 {
   struct bfin_sic *sic = hw_data (me);
-  bu32 idx = my_port / 100;
-  bu32 bit = (1 << (my_port & 0x1f));
+  bu32 idx = DEC_SIC (my_port);
+  bu32 bit = 1 << DEC_PIN (my_port);
 
   /* SIC only exists to forward interrupts from the system to the CEC.  */
   switch (idx)
@@ -1091,71 +1082,71 @@ static const struct hw_port_descriptor bfin_sic_561_ports[] =
 {
   BFIN_SIC_TO_CEC_PORTS
   /* SIC0 */
-  { "pll",            0, 0, input_port, },
-  { "dmac@0_stat",    1, 0, input_port, },
-  { "dmac@1_stat",    2, 0, input_port, },
-  { "imdma_stat",     3, 0, input_port, },
-  { "ppi@0",          4, 0, input_port, },
-  { "ppi@1",          5, 0, input_port, },
-  { "sport@0_stat",   6, 0, input_port, },
-  { "sport@1_stat",   7, 0, input_port, },
-  { "spi@0",          8, 0, input_port, },
-  { "uart@0_stat",    9, 0, input_port, },
-/*{ "reserved",      10, 0, input_port, },*/
-  { "dma@12",        11, 0, input_port, },
-  { "dma@13",        12, 0, input_port, },
-  { "dma@14",        13, 0, input_port, },
-  { "dma@15",        14, 0, input_port, },
-  { "dma@16",        15, 0, input_port, },
-  { "dma@17",        16, 0, input_port, },
-  { "dma@18",        17, 0, input_port, },
-  { "dma@19",        18, 0, input_port, },
-  { "dma@20",        19, 0, input_port, },
-  { "dma@21",        20, 0, input_port, },
-  { "dma@22",        21, 0, input_port, },
-  { "dma@23",        22, 0, input_port, },
-  { "dma@0",         23, 0, input_port, },
-  { "dma@1",         24, 0, input_port, },
-  { "dma@2",         25, 0, input_port, },
-  { "dma@3",         26, 0, input_port, },
-  { "dma@4",         27, 0, input_port, },
-  { "dma@5",         28, 0, input_port, },
-  { "dma@6",         29, 0, input_port, },
-  { "dma@7",         30, 0, input_port, },
-  { "dma@8",         31, 0, input_port, },
+  { "pll",             ENC(0,  0), 0, input_port, },
+  { "dmac@0_stat",     ENC(0,  1), 0, input_port, },
+  { "dmac@1_stat",     ENC(0,  2), 0, input_port, },
+  { "imdma_stat",      ENC(0,  3), 0, input_port, },
+  { "ppi@0",           ENC(0,  4), 0, input_port, },
+  { "ppi@1",           ENC(0,  5), 0, input_port, },
+  { "sport@0_stat",    ENC(0,  6), 0, input_port, },
+  { "sport@1_stat",    ENC(0,  7), 0, input_port, },
+  { "spi@0",           ENC(0,  8), 0, input_port, },
+  { "uart@0_stat",     ENC(0,  9), 0, input_port, },
+/*{ "reserved",        ENC(0, 10), 0, input_port, },*/
+  { "dma@12",          ENC(0, 11), 0, input_port, },
+  { "dma@13",          ENC(0, 12), 0, input_port, },
+  { "dma@14",          ENC(0, 13), 0, input_port, },
+  { "dma@15",          ENC(0, 14), 0, input_port, },
+  { "dma@16",          ENC(0, 15), 0, input_port, },
+  { "dma@17",          ENC(0, 16), 0, input_port, },
+  { "dma@18",          ENC(0, 17), 0, input_port, },
+  { "dma@19",          ENC(0, 18), 0, input_port, },
+  { "dma@20",          ENC(0, 19), 0, input_port, },
+  { "dma@21",          ENC(0, 20), 0, input_port, },
+  { "dma@22",          ENC(0, 21), 0, input_port, },
+  { "dma@23",          ENC(0, 22), 0, input_port, },
+  { "dma@0",           ENC(0, 23), 0, input_port, },
+  { "dma@1",           ENC(0, 24), 0, input_port, },
+  { "dma@2",           ENC(0, 25), 0, input_port, },
+  { "dma@3",           ENC(0, 26), 0, input_port, },
+  { "dma@4",           ENC(0, 27), 0, input_port, },
+  { "dma@5",           ENC(0, 28), 0, input_port, },
+  { "dma@6",           ENC(0, 29), 0, input_port, },
+  { "dma@7",           ENC(0, 30), 0, input_port, },
+  { "dma@8",           ENC(0, 31), 0, input_port, },
   /* SIC1 */
-  { "dma@9",        100, 0, input_port, },
-  { "dma@10",       101, 0, input_port, },
-  { "dma@11",       102, 0, input_port, },
-  { "gptimer@0",    103, 0, input_port, },
-  { "gptimer@1",    104, 0, input_port, },
-  { "gptimer@2",    105, 0, input_port, },
-  { "gptimer@3",    106, 0, input_port, },
-  { "gptimer@4",    107, 0, input_port, },
-  { "gptimer@5",    108, 0, input_port, },
-  { "gptimer@6",    109, 0, input_port, },
-  { "gptimer@7",    110, 0, input_port, },
-  { "gptimer@8",    111, 0, input_port, },
-  { "gptimer@9",    112, 0, input_port, },
-  { "gptimer@10",   113, 0, input_port, },
-  { "gptimer@11",   114, 0, input_port, },
-  { "portf_irq_a",  115, 0, input_port, },
-  { "portf_irq_b",  116, 0, input_port, },
-  { "portg_irq_a",  117, 0, input_port, },
-  { "portg_irq_b",  118, 0, input_port, },
-  { "porth_irq_a",  119, 0, input_port, },
-  { "porth_irq_b",  120, 0, input_port, },
-  { "mdma@0",       121, 0, input_port, },
-  { "mdma@1",       122, 0, input_port, },
-  { "mdma@2",       123, 0, input_port, },
-  { "mdma@3",       124, 0, input_port, },
-  { "imdma@0",      125, 0, input_port, },
-  { "imdma@1",      126, 0, input_port, },
-  { "wdog",         127, 0, input_port, },
-/*{ "reserved",     128, 0, input_port, },*/
-/*{ "reserved",     129, 0, input_port, },*/
-  { "sup_irq_0",    130, 0, input_port, },
-  { "sup_irq_1",    131, 0, input_port, },
+  { "dma@9",           ENC(1,  0), 0, input_port, },
+  { "dma@10",          ENC(1,  1), 0, input_port, },
+  { "dma@11",          ENC(1,  2), 0, input_port, },
+  { "gptimer@0",       ENC(1,  3), 0, input_port, },
+  { "gptimer@1",       ENC(1,  4), 0, input_port, },
+  { "gptimer@2",       ENC(1,  5), 0, input_port, },
+  { "gptimer@3",       ENC(1,  6), 0, input_port, },
+  { "gptimer@4",       ENC(1,  7), 0, input_port, },
+  { "gptimer@5",       ENC(1,  8), 0, input_port, },
+  { "gptimer@6",       ENC(1,  9), 0, input_port, },
+  { "gptimer@7",       ENC(1, 10), 0, input_port, },
+  { "gptimer@8",       ENC(1, 11), 0, input_port, },
+  { "gptimer@9",       ENC(1, 12), 0, input_port, },
+  { "gptimer@10",      ENC(1, 13), 0, input_port, },
+  { "gptimer@11",      ENC(1, 14), 0, input_port, },
+  { "portf_irq_a",     ENC(1, 15), 0, input_port, },
+  { "portf_irq_b",     ENC(1, 16), 0, input_port, },
+  { "portg_irq_a",     ENC(1, 17), 0, input_port, },
+  { "portg_irq_b",     ENC(1, 18), 0, input_port, },
+  { "porth_irq_a",     ENC(1, 19), 0, input_port, },
+  { "porth_irq_b",     ENC(1, 20), 0, input_port, },
+  { "mdma@0",          ENC(1, 21), 0, input_port, },
+  { "mdma@1",          ENC(1, 22), 0, input_port, },
+  { "mdma@2",          ENC(1, 23), 0, input_port, },
+  { "mdma@3",          ENC(1, 24), 0, input_port, },
+  { "imdma@0",         ENC(1, 25), 0, input_port, },
+  { "imdma@1",         ENC(1, 26), 0, input_port, },
+  { "wdog",            ENC(1, 27), 0, input_port, },
+/*{ "reserved",        ENC(1, 28), 0, input_port, },*/
+/*{ "reserved",        ENC(1, 29), 0, input_port, },*/
+  { "sup_irq_0",       ENC(1, 30), 0, input_port, },
+  { "sup_irq_1",       ENC(1, 31), 0, input_port, },
   { NULL, 0, 0, 0, },
 };
 
@@ -1164,8 +1155,8 @@ bfin_sic_561_port_event (struct hw *me, int my_port, struct hw *source,
 			 int source_port, int level)
 {
   struct bfin_sic *sic = hw_data (me);
-  bu32 idx = my_port / 100;
-  bu32 bit = (1 << (my_port & 0x1f));
+  bu32 idx = DEC_SIC (my_port);
+  bu32 bit = 1 << DEC_PIN (my_port);
 
   /* SIC only exists to forward interrupts from the system to the CEC.  */
   switch (idx)
@@ -1187,43 +1178,43 @@ bfin_sic_561_port_event (struct hw *me, int my_port, struct hw *source,
 static const struct hw_port_descriptor bfin_sic_59x_ports[] =
 {
   BFIN_SIC_TO_CEC_PORTS
-  { "pll",            0, 0, input_port, },
-  { "dma_stat",       1, 0, input_port, },
-  { "ppi@0",          2, 0, input_port, },
-  { "sport@0_stat",   3, 0, input_port, },
-  { "sport@1_stat",   4, 0, input_port, },
-  { "spi@0",          5, 0, input_port, },
-  { "spi@1",          6, 0, input_port, },
-  { "uart@0_stat",    7, 0, input_port, },
-  { "dma@0",          8, 0, input_port, },
-  { "dma@1",          9, 0, input_port, },
-  { "dma@2",         10, 0, input_port, },
-  { "dma@3",         11, 0, input_port, },
-  { "dma@4",         12, 0, input_port, },
-  { "dma@5",         13, 0, input_port, },
-  { "dma@6",         14, 0, input_port, },
-  { "dma@7",         15, 0, input_port, },
-  { "dma@8",         16, 0, input_port, },
-  { "portf_irq_a",   17, 0, input_port, },
-  { "portf_irq_b",   18, 0, input_port, },
-  { "gptimer@0",     19, 0, input_port, },
-  { "gptimer@1",     20, 0, input_port, },
-  { "gptimer@2",     21, 0, input_port, },
-  { "portg_irq_a",   22, 0, input_port, },
-  { "portg_irq_b",   23, 0, input_port, },
-  { "twi@0",         24, 0, input_port, },
+  { "pll",             ENC(0,  0), 0, input_port, },
+  { "dma_stat",        ENC(0,  1), 0, input_port, },
+  { "ppi@0",           ENC(0,  2), 0, input_port, },
+  { "sport@0_stat",    ENC(0,  3), 0, input_port, },
+  { "sport@1_stat",    ENC(0,  4), 0, input_port, },
+  { "spi@0",           ENC(0,  5), 0, input_port, },
+  { "spi@1",           ENC(0,  6), 0, input_port, },
+  { "uart@0_stat",     ENC(0,  7), 0, input_port, },
+  { "dma@0",           ENC(0,  8), 0, input_port, },
+  { "dma@1",           ENC(0,  9), 0, input_port, },
+  { "dma@2",           ENC(0, 10), 0, input_port, },
+  { "dma@3",           ENC(0, 11), 0, input_port, },
+  { "dma@4",           ENC(0, 12), 0, input_port, },
+  { "dma@5",           ENC(0, 13), 0, input_port, },
+  { "dma@6",           ENC(0, 14), 0, input_port, },
+  { "dma@7",           ENC(0, 15), 0, input_port, },
+  { "dma@8",           ENC(0, 16), 0, input_port, },
+  { "portf_irq_a",     ENC(0, 17), 0, input_port, },
+  { "portf_irq_b",     ENC(0, 18), 0, input_port, },
+  { "gptimer@0",       ENC(0, 19), 0, input_port, },
+  { "gptimer@1",       ENC(0, 20), 0, input_port, },
+  { "gptimer@2",       ENC(0, 21), 0, input_port, },
+  { "portg_irq_a",     ENC(0, 22), 0, input_port, },
+  { "portg_irq_b",     ENC(0, 23), 0, input_port, },
+  { "twi@0",           ENC(0, 24), 0, input_port, },
 /* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[]  */
-  { "dma@9",         25, 0, input_port, },
-  { "dma@10",        26, 0, input_port, },
-  { "dma@11",        27, 0, input_port, },
-  { "dma@12",        28, 0, input_port, },
-/*{ "reserved",      25, 0, input_port, },*/
-/*{ "reserved",      26, 0, input_port, },*/
-/*{ "reserved",      27, 0, input_port, },*/
-/*{ "reserved",      28, 0, input_port, },*/
-  { "mdma@0",        29, 0, input_port, },
-  { "mdma@1",        30, 0, input_port, },
-  { "wdog",          31, 0, input_port, },
+  { "dma@9",           ENC(0, 25), 0, input_port, },
+  { "dma@10",          ENC(0, 26), 0, input_port, },
+  { "dma@11",          ENC(0, 27), 0, input_port, },
+  { "dma@12",          ENC(0, 28), 0, input_port, },
+/*{ "reserved",        ENC(0, 25), 0, input_port, },*/
+/*{ "reserved",        ENC(0, 26), 0, input_port, },*/
+/*{ "reserved",        ENC(0, 27), 0, input_port, },*/
+/*{ "reserved",        ENC(0, 28), 0, input_port, },*/
+  { "mdma@0",          ENC(0, 29), 0, input_port, },
+  { "mdma@1",          ENC(0, 30), 0, input_port, },
+  { "wdog",            ENC(0, 31), 0, input_port, },
   { NULL, 0, 0, 0, },
 };
 
@@ -1331,7 +1322,7 @@ bfin_sic_finish (struct hw *me)
       set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
       set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
       set_hw_ports (me, bfin_sic_533_ports);
-      set_hw_port_event (me, bfin_sic_533_port_event);
+      set_hw_port_event (me, bfin_sic_537_port_event);
       mmr_names = bf537_mmr_names;
 
       /* Initialize the SIC.  */
@@ -1429,7 +1420,7 @@ bfin_sic_finish (struct hw *me)
       set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
       set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
       set_hw_ports (me, bfin_sic_59x_ports);
-      set_hw_port_event (me, bfin_sic_533_port_event);
+      set_hw_port_event (me, bfin_sic_537_port_event);
       mmr_names = bf537_mmr_names;
 
       /* Initialize the SIC.  */