diff options
| -rw-r--r-- | include/ChangeLog | 14 | ||||
| -rw-r--r-- | include/dwarf2.def | 8 | ||||
| -rw-r--r-- | include/longlong.h | 50 |
3 files changed, 72 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index fe1d6c9f656..b8a0a2324d7 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,17 @@ +2018-06-19 Simon Marchi <simon.marchi@ericsson.com> + + Sync with GCC + + 2018-05-24 Tom Rix <trix@juniper.net> + + * dwarf2.def (DW_FORM_strx*, DW_FORM_addrx*): New. + + 2017-11-20 Kito Cheng <kito.cheng@gmail.com> + + * longlong.h [__riscv] (__umulsidi3): Define. + [__riscv] (umul_ppmm): Likewise. + [__riscv] (__muluw3): Likewise. + 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com> * elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros. diff --git a/include/dwarf2.def b/include/dwarf2.def index 3becd7f8219..358844f9bf8 100644 --- a/include/dwarf2.def +++ b/include/dwarf2.def @@ -220,6 +220,14 @@ DW_FORM (DW_FORM_implicit_const, 0x21) DW_FORM (DW_FORM_loclistx, 0x22) DW_FORM (DW_FORM_rnglistx, 0x23) DW_FORM (DW_FORM_ref_sup8, 0x24) +DW_FORM (DW_FORM_strx1, 0x25) +DW_FORM (DW_FORM_strx2, 0x26) +DW_FORM (DW_FORM_strx3, 0x27) +DW_FORM (DW_FORM_strx4, 0x28) +DW_FORM (DW_FORM_addrx1, 0x29) +DW_FORM (DW_FORM_addrx2, 0x2a) +DW_FORM (DW_FORM_addrx3, 0x2b) +DW_FORM (DW_FORM_addrx4, 0x2c) /* Extensions for Fission. See http://gcc.gnu.org/wiki/DebugFission. */ DW_FORM (DW_FORM_GNU_addr_index, 0x1f01) DW_FORM (DW_FORM_GNU_str_index, 0x1f02) diff --git a/include/longlong.h b/include/longlong.h index fb982dd530c..7f3dc17dc0a 100644 --- a/include/longlong.h +++ b/include/longlong.h @@ -1050,6 +1050,56 @@ extern UDItype __umulsidi3 (USItype, USItype); } while (0) #endif +#if defined(__riscv) +#ifdef __riscv_mul +#define __umulsidi3(u,v) ((UDWtype)(UWtype)(u) * (UWtype)(v)) +#define __muluw3(a, b) ((UWtype)(a) * (UWtype)(b)) +#else +#if __riscv_xlen == 32 + #define MULUW3 "call __mulsi3" +#elif __riscv_xlen == 64 + #define MULUW3 "call __muldi3" +#else +#error unsupport xlen +#endif /* __riscv_xlen */ +/* We rely on the fact that MULUW3 doesn't clobber the t-registers. + It can get better register allocation result. */ +#define __muluw3(a, b) \ + ({ \ + register UWtype __op0 asm ("a0") = a; \ + register UWtype __op1 asm ("a1") = b; \ + asm volatile (MULUW3 \ + : "+r" (__op0), "+r" (__op1) \ + : \ + : "ra", "a2", "a3"); \ + __op0; \ + }) +#endif /* __riscv_mul */ +#define umul_ppmm(w1, w0, u, v) \ + do { \ + UWtype __x0, __x1, __x2, __x3; \ + UHWtype __ul, __vl, __uh, __vh; \ + \ + __ul = __ll_lowpart (u); \ + __uh = __ll_highpart (u); \ + __vl = __ll_lowpart (v); \ + __vh = __ll_highpart (v); \ + \ + __x0 = __muluw3 (__ul, __vl); \ + __x1 = __muluw3 (__ul, __vh); \ + __x2 = __muluw3 (__uh, __vl); \ + __x3 = __muluw3 (__uh, __vh); \ + \ + __x1 += __ll_highpart (__x0);/* this can't give carry */ \ + __x1 += __x2; /* but this indeed can */ \ + if (__x1 < __x2) /* did we get it? */ \ + __x3 += __ll_B; /* yes, add it in the proper pos. */ \ + \ + (w1) = __x3 + __ll_highpart (__x1); \ + (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \ + } while (0) +#endif /* __riscv */ + #if defined(__sh__) && W_TYPE_SIZE == 32 #ifndef __sh1__ #define umul_ppmm(w1, w0, u, v) \ |