diff options
Diffstat (limited to 'gas/config/tc-mips.c')
| -rw-r--r-- | gas/config/tc-mips.c | 670 |
1 files changed, 129 insertions, 541 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index beaa11a5aaf..6f0db0912ff 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -111,9 +111,7 @@ static char *mips_regmask_frag; extern int target_big_endian; /* The name of the readonly data section. */ -#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ - ? ".data" \ - : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ +#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ ? ".rdata" \ : OUTPUT_FLAVOR == bfd_target_coff_flavour \ ? ".rdata" \ @@ -281,13 +279,11 @@ static int mips_32bitmode = 0; #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) -/* We can only have 64bit addresses if the object file format - supports it. */ +/* We can only have 64bit addresses if the object file format supports it. */ #define HAVE_32BIT_ADDRESSES \ (HAVE_32BIT_GPRS \ - || ((bfd_arch_bits_per_address (stdoutput) == 32 \ - || ! HAVE_64BIT_OBJECTS) \ - && mips_pic != EMBEDDED_PIC)) + || (bfd_arch_bits_per_address (stdoutput) == 32 \ + || ! HAVE_64BIT_OBJECTS)) \ #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) @@ -346,7 +342,6 @@ static int mips_32bitmode = 0; || mips_opts.arch == CPU_R10000 \ || mips_opts.arch == CPU_R12000 \ || mips_opts.arch == CPU_RM7000 \ - || mips_opts.arch == CPU_SB1 \ || mips_opts.arch == CPU_VR5500 \ ) @@ -357,8 +352,6 @@ static int mips_32bitmode = 0; level I. */ #define gpr_interlocks \ (mips_opts.isa != ISA_MIPS1 \ - || mips_opts.arch == CPU_VR5400 \ - || mips_opts.arch == CPU_VR5500 \ || mips_opts.arch == CPU_R3900) /* Whether the processor uses hardware interlocks to avoid delays @@ -374,9 +367,6 @@ static int mips_32bitmode = 0; && mips_opts.isa != ISA_MIPS2 \ && mips_opts.isa != ISA_MIPS3) \ || mips_opts.arch == CPU_R4300 \ - || mips_opts.arch == CPU_VR5400 \ - || mips_opts.arch == CPU_VR5500 \ - || mips_opts.arch == CPU_SB1 \ ) /* Whether the processor uses hardware interlocks to protect reads @@ -622,7 +612,7 @@ static const unsigned int mips16_to_32_reg_map[] = 16, 17, 2, 3, 4, 5, 6, 7 }; -static int mips_fix_4122_bugs; +static int mips_fix_vr4120; /* We don't relax branches by default, since this causes us to expand `la .l2 - .l1' if there's a branch between .l1 and .l2, because we @@ -1089,8 +1079,6 @@ mips_target_format (void) { switch (OUTPUT_FLAVOR) { - case bfd_target_aout_flavour: - return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; case bfd_target_ecoff_flavour: return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; case bfd_target_coff_flavour: @@ -1247,8 +1235,7 @@ md_begin (void) /* set the default alignment for the text section (2**2) */ record_alignment (text_section, 2); - if (USE_GLOBAL_POINTER_OPT) - bfd_set_gp_size (stdoutput, g_switch_value); + bfd_set_gp_size (stdoutput, g_switch_value); if (OUTPUT_FLAVOR == bfd_target_elf_flavour) { @@ -1863,11 +1850,11 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr, if (prev_prev_nop && nops == 0) ++nops; - if (mips_fix_4122_bugs && prev_insn.insn_mo->name) + if (mips_fix_vr4120 && prev_insn.insn_mo->name) { /* We're out of bits in pinfo, so we must resort to string ops here. Shortcuts are selected based on opcodes being - limited to the VR4122 instruction set. */ + limited to the VR4120 instruction set. */ int min_nops = 0; const char *pn = prev_insn.insn_mo->name; const char *tn = ip->insn_mo->name; @@ -2494,11 +2481,6 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr, || (mips_opts.mips16 && (pinfo & MIPS16_INSN_WRITE_31) && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) - /* If we are generating embedded PIC code, the branch - might be expanded into a sequence which uses $at, so - we can't swap with an instruction which reads it. */ - || (mips_pic == EMBEDDED_PIC - && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) /* If the previous previous instruction has a load delay, and sets a register that the branch reads, we can not swap. */ @@ -2841,7 +2823,7 @@ mips_emit_delays (bfd_boolean insns) ++nops; } - if (mips_fix_4122_bugs && prev_insn.insn_mo->name) + if (mips_fix_vr4120 && prev_insn.insn_mo->name) { int min_nops = 0; const char *pn = prev_insn.insn_mo->name; @@ -3143,9 +3125,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...) || *r == BFD_RELOC_MIPS_GOT_PAGE || *r == BFD_RELOC_MIPS_GOT_OFST || *r == BFD_RELOC_MIPS_GOT_LO16 - || *r == BFD_RELOC_MIPS_CALL_LO16 - || (ep->X_op == O_subtract - && *r == BFD_RELOC_PCREL_LO16)); + || *r == BFD_RELOC_MIPS_CALL_LO16); continue; case 'u': @@ -3158,9 +3138,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...) || *r == BFD_RELOC_HI16 || *r == BFD_RELOC_GPREL16 || *r == BFD_RELOC_MIPS_GOT_HI16 - || *r == BFD_RELOC_MIPS_CALL_HI16)) - || (ep->X_op == O_subtract - && *r == BFD_RELOC_PCREL_HI16_S))); + || *r == BFD_RELOC_MIPS_CALL_HI16)))); continue; case 'p': @@ -3789,6 +3767,13 @@ load_register (int reg, expressionS *ep, int dbl) macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); } +static inline void +load_delay_nop (void) +{ + if (!gpr_interlocks) + macro_build (NULL, "nop", ""); +} + /* Load an address into a register. */ static void @@ -3922,7 +3907,7 @@ load_address (int reg, expressionS *ep, int *used_at) ep->X_add_number = 0; macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, BFD_RELOC_MIPS_GOT16, mips_gp_register); - macro_build (NULL, "nop", ""); + load_delay_nop (); relax_start (ep->X_add_symbol); relax_switch (); macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, @@ -4007,7 +3992,7 @@ load_address (int reg, expressionS *ep, int *used_at) } macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, BFD_RELOC_MIPS_GOT16, mips_gp_register); - macro_build (NULL, "nop", ""); + load_delay_nop (); macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, BFD_RELOC_LO16); relax_end (); @@ -4022,14 +4007,6 @@ load_address (int reg, expressionS *ep, int *used_at) } } } - else if (mips_pic == EMBEDDED_PIC) - { - /* We always do - addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) - */ - macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", - reg, mips_gp_register, BFD_RELOC_GPREL16); - } else abort (); } @@ -4888,50 +4865,6 @@ macro (struct mips_cl_insn *ip) used_at = 0; } - /* When generating embedded PIC code, we permit expressions of - the form - la $treg,foo-bar - la $treg,foo-bar($breg) - where bar is an address in the current section. These are used - when getting the addresses of functions. We don't permit - X_add_number to be non-zero, because if the symbol is - external the relaxing code needs to know that any addend is - purely the offset to X_op_symbol. */ - if (mips_pic == EMBEDDED_PIC - && offset_expr.X_op == O_subtract - && (symbol_constant_p (offset_expr.X_op_symbol) - ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg - : (symbol_equated_p (offset_expr.X_op_symbol) - && (S_GET_SEGMENT - (symbol_get_value_expression (offset_expr.X_op_symbol) - ->X_add_symbol) - == now_seg))) - && (offset_expr.X_add_number == 0 - || OUTPUT_FLAVOR == bfd_target_elf_flavour)) - { - if (breg == 0) - { - tempreg = treg; - used_at = 0; - macro_build (&offset_expr, "lui", "t,u", - tempreg, BFD_RELOC_PCREL_HI16_S); - } - else - { - macro_build (&offset_expr, "lui", "t,u", - tempreg, BFD_RELOC_PCREL_HI16_S); - macro_build (NULL, - (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", - "d,v,t", tempreg, tempreg, breg); - } - macro_build (&offset_expr, - (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", - "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16); - if (! used_at) - return; - break; - } - if (offset_expr.X_op != O_symbol && offset_expr.X_op != O_constant) { @@ -4941,7 +4874,7 @@ macro (struct mips_cl_insn *ip) if (offset_expr.X_op == O_constant) load_register (tempreg, &offset_expr, - ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) + (mips_pic == NO_PIC ? (dbl || HAVE_64BIT_ADDRESSES) : HAVE_64BIT_ADDRESSES)); else if (mips_pic == NO_PIC) @@ -5069,12 +5002,12 @@ macro (struct mips_cl_insn *ip) /* We're going to put in an addu instruction using tempreg, so we may as well insert the nop right now. */ - macro_build (NULL, "nop", ""); + load_delay_nop (); } relax_switch (); macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); - macro_build (NULL, "nop", ""); + load_delay_nop (); macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); relax_end (); @@ -5086,7 +5019,7 @@ macro (struct mips_cl_insn *ip) && offset_expr.X_add_number < 0x8000) { load_got_offset (tempreg, &offset_expr); - macro_build (NULL, "nop", ""); + load_delay_nop (); add_got_offset (tempreg, &offset_expr); } else @@ -5105,7 +5038,7 @@ macro (struct mips_cl_insn *ip) not using a base register. */ if (breg == treg) { - macro_build (NULL, "nop", ""); + load_delay_nop (); macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg); breg = 0; @@ -5288,13 +5221,13 @@ macro (struct mips_cl_insn *ip) /* We're going to put in an addu instruction using tempreg, so we may as well insert the nop right now. */ - macro_build (NULL, "nop", ""); + load_delay_nop (); } } else if (expr1.X_add_number >= -0x8000 && expr1.X_add_number < 0x8000) { - macro_build (NULL, "nop", ""); + load_delay_nop (); macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); } @@ -5314,7 +5247,7 @@ macro (struct mips_cl_insn *ip) else { assert (tempreg == AT); - macro_build (NULL, "nop", ""); + load_delay_nop (); macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg); dreg = treg; @@ -5341,7 +5274,7 @@ macro (struct mips_cl_insn *ip) if (expr1.X_add_number >= -0x8000 && expr1.X_add_number < 0x8000) { - macro_build (NULL, "nop", ""); + load_delay_nop (); macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); /* FIXME: If add_number is 0, and there was no base @@ -5357,7 +5290,7 @@ macro (struct mips_cl_insn *ip) /* We must add in the base register now, as in the external symbol case. */ assert (tempreg == AT); - macro_build (NULL, "nop", ""); + load_delay_nop (); macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, AT, breg); tempreg = treg; @@ -5481,14 +5414,6 @@ macro (struct mips_cl_insn *ip) } relax_end (); } - else if (mips_pic == EMBEDDED_PIC) - { - /* We use - addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) - */ - macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, - mips_gp_register, BFD_RELOC_GPREL16); - } else abort (); @@ -5496,7 +5421,7 @@ macro (struct mips_cl_insn *ip) { char *s; - if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) + if (mips_pic == NO_PIC) s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; else s = ADDRESS_ADD_INSN; @@ -5526,8 +5451,7 @@ macro (struct mips_cl_insn *ip) dreg = RA; /* Fall through. */ case M_JAL_2: - if (mips_pic == NO_PIC - || mips_pic == EMBEDDED_PIC) + if (mips_pic == NO_PIC) macro_build (NULL, "jalr", "d,s", dreg, sreg); else if (mips_pic == SVR4_PIC) { @@ -5643,7 +5567,7 @@ macro (struct mips_cl_insn *ip) macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, mips_gp_register); - macro_build (NULL, "nop", ""); + load_delay_nop (); relax_switch (); } else @@ -5658,7 +5582,7 @@ macro (struct mips_cl_insn *ip) macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); - macro_build (NULL, "nop", ""); + load_delay_nop (); relax_switch (); if (gpdelay) macro_build (NULL, "nop", ""); @@ -5666,7 +5590,7 @@ macro (struct mips_cl_insn *ip) macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, mips_gp_register); - macro_build (NULL, "nop", ""); + load_delay_nop (); macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); relax_end (); @@ -5698,13 +5622,6 @@ macro (struct mips_cl_insn *ip) } } } - else if (mips_pic == EMBEDDED_PIC) - { - macro_build (&offset_expr, "bal", "p"); - /* The linker may expand the call to a longer sequence which - uses $at, so we must break rather than return. */ - break; - } else abort (); @@ -5900,46 +5817,6 @@ macro (struct mips_cl_insn *ip) ^ 0x80000000) - 0x80000000); } - /* For embedded PIC, we allow loads where the offset is calculated - by subtracting a symbol in the current segment from an unknown - symbol, relative to a base register, e.g.: - <op> $treg, <sym>-<localsym>($breg) - This is used by the compiler for switch statements. */ - if (mips_pic == EMBEDDED_PIC - && offset_expr.X_op == O_subtract - && (symbol_constant_p (offset_expr.X_op_symbol) - ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg - : (symbol_equated_p (offset_expr.X_op_symbol) - && (S_GET_SEGMENT - (symbol_get_value_expression (offset_expr.X_op_symbol) - ->X_add_symbol) - == now_seg))) - && breg != 0 - && (offset_expr.X_add_number == 0 - || OUTPUT_FLAVOR == bfd_target_elf_flavour)) - { - /* For this case, we output the instructions: - lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) - addiu $tempreg,$tempreg,$breg - <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) - If the relocation would fit entirely in 16 bits, it would be - nice to emit: - <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) - instead, but that seems quite difficult. */ - macro_build (&offset_expr, "lui", "t,u", tempreg, - BFD_RELOC_PCREL_HI16_S); - macro_build (NULL, - ((bfd_arch_bits_per_address (stdoutput) == 32 - || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) - ? "addu" : "daddu"), - "d,v,t", tempreg, tempreg, breg); - macro_build (&offset_expr, s, fmt, treg, - BFD_RELOC_PCREL_LO16, tempreg); - if (! used_at) - return; - break; - } - if (offset_expr.X_op != O_constant && offset_expr.X_op != O_symbol) { @@ -6166,7 +6043,7 @@ macro (struct mips_cl_insn *ip) as_bad (_("PIC code offset overflow (max 16 signed bits)")); macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, lw_reloc_type, mips_gp_register); - macro_build (NULL, "nop", ""); + load_delay_nop (); relax_start (offset_expr.X_add_symbol); relax_switch (); macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, @@ -6216,7 +6093,7 @@ macro (struct mips_cl_insn *ip) macro_build (NULL, "nop", ""); macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); - macro_build (NULL, "nop", ""); + load_delay_nop (); macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); relax_end (); @@ -6265,29 +6142,6 @@ macro (struct mips_cl_insn *ip) BFD_RELOC_MIPS_GOT_OFST, tempreg); relax_end (); } - else if (mips_pic == EMBEDDED_PIC) - { - /* If there is no base register, we want - <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) - If there is a base register, we want - addu $tempreg,$breg,$gp - <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) - */ - assert (offset_expr.X_op == O_symbol); - if (breg == 0) - { - macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, - mips_gp_register); - used_at = 0; - } - else - { - macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", - tempreg, breg, mips_gp_register); - macro_build (&offset_expr, s, fmt, treg, - BFD_RELOC_GPREL16, tempreg); - } - } else abort (); @@ -6375,15 +6229,6 @@ macro (struct mips_cl_insn *ip) macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, BFD_RELOC_MIPS_GOT16, mips_gp_register); } - else if (mips_pic == EMBEDDED_PIC) - { - /* For embedded PIC we pick up the entire address off $gp in - a single instruction. */ - macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, - mips_gp_register, BFD_RELOC_GPREL16); - offset_expr.X_op = O_constant; - offset_expr.X_add_number = 0; - } else abort (); @@ -6564,11 +6409,6 @@ macro (struct mips_cl_insn *ip) fmt = "t,o(b)"; ldd_std: - /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) - loads for the case of doing a pair of loads to simulate an 'ld'. - This is not currently done by the compiler, and assembly coders - writing embedded-pic code can cope. */ - if (offset_expr.X_op != O_symbol && offset_expr.X_op != O_constant) { @@ -6691,7 +6531,7 @@ macro (struct mips_cl_insn *ip) || expr1.X_add_number >= 0x8000 - 4) as_bad (_("PIC code offset overflow (max 16 signed bits)")); load_got_offset (AT, &offset_expr); - macro_build (NULL, "nop", ""); + load_delay_nop (); if (breg != 0) macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); @@ -6750,7 +6590,7 @@ macro (struct mips_cl_insn *ip) AT, AT, mips_gp_register); macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, BFD_RELOC_MIPS_GOT_LO16, AT); - macro_build (NULL, "nop", ""); + load_delay_nop (); if (breg != 0) macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); /* Itbl support may require additional care here. */ @@ -6774,7 +6614,7 @@ macro (struct mips_cl_insn *ip) macro_build (NULL, "nop", ""); macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, BFD_RELOC_MIPS_GOT16, mips_gp_register); - macro_build (NULL, "nop", ""); + load_delay_nop (); if (breg != 0) macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); /* Itbl support may require additional care here. */ @@ -6792,37 +6632,6 @@ macro (struct mips_cl_insn *ip) mips_optimize = hold_mips_optimize; relax_end (); } - else if (mips_pic == EMBEDDED_PIC) - { - /* If there is no base register, we use - <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) - <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) - If we have a base register, we use - addu $at,$breg,$gp - <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) - <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) - */ - if (breg == 0) - { - tempreg = mips_gp_register; - used_at = 0; - } - else - { - macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", - AT, breg, mips_gp_register); - tempreg = AT; - used_at = 1; - } - - /* Itbl support may require additional care here. */ - macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, - BFD_RELOC_GPREL16, tempreg); - offset_expr.X_add_number += 4; - /* Itbl support may require additional care here. */ - macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, - BFD_RELOC_GPREL16, tempreg); - } else abort (); @@ -7553,8 +7362,7 @@ macro2 (struct mips_cl_insn *ip) if (treg == tempreg) return; /* Protect second load's delay slot. */ - if (!gpr_interlocks) - macro_build (NULL, "nop", ""); + load_delay_nop (); move_register (treg, tempreg); break; @@ -8862,13 +8670,6 @@ do_msbd: The .lit4 and .lit8 sections are only used if permitted by the -G argument. - When generating embedded PIC code, we use the - .lit8 section but not the .lit4 section (we can do - .lit4 inline easily; we need to put .lit8 - somewhere in the data segment, and using .lit8 - permits the linker to eventually combine identical - .lit8 entries). - The code below needs to know whether the target register is 32 or 64 bits wide. It relies on the fact 'f' and 'F' are used with GPR-based instructions and 'l' and @@ -8894,9 +8695,7 @@ do_msbd: if (*args == 'f' || (*args == 'l' - && (! USE_GLOBAL_POINTER_OPT - || mips_pic == EMBEDDED_PIC - || g_switch_value < 4 + && (g_switch_value < 4 || (temp[0] == 0 && temp[1] == 0) || (temp[2] == 0 && temp[3] == 0)))) { @@ -8983,19 +8782,14 @@ do_msbd: default: /* unused default case avoids warnings. */ case 'L': newname = RDATA_SECTION_NAME; - if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) - || mips_pic == EMBEDDED_PIC) + if (g_switch_value >= 8) newname = ".lit8"; break; case 'F': - if (mips_pic == EMBEDDED_PIC) - newname = ".lit8"; - else - newname = RDATA_SECTION_NAME; + newname = RDATA_SECTION_NAME; break; case 'l': - assert (!USE_GLOBAL_POINTER_OPT - || g_switch_value >= 4); + assert (g_switch_value >= 4); newname = ".lit4"; break; } @@ -10254,45 +10048,43 @@ struct option md_longopts[] = #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, -#define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2) -#define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3) - {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122}, - {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122}, +#define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) +#define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) + {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, + {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, /* Miscellaneous options. */ #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) -#define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0) - {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, -#define OPTION_TRAP (OPTION_MISC_BASE + 1) +#define OPTION_TRAP (OPTION_MISC_BASE + 0) {"trap", no_argument, NULL, OPTION_TRAP}, {"no-break", no_argument, NULL, OPTION_TRAP}, -#define OPTION_BREAK (OPTION_MISC_BASE + 2) +#define OPTION_BREAK (OPTION_MISC_BASE + 1) {"break", no_argument, NULL, OPTION_BREAK}, {"no-trap", no_argument, NULL, OPTION_BREAK}, -#define OPTION_EB (OPTION_MISC_BASE + 3) +#define OPTION_EB (OPTION_MISC_BASE + 2) {"EB", no_argument, NULL, OPTION_EB}, -#define OPTION_EL (OPTION_MISC_BASE + 4) +#define OPTION_EL (OPTION_MISC_BASE + 3) {"EL", no_argument, NULL, OPTION_EL}, -#define OPTION_FP32 (OPTION_MISC_BASE + 5) +#define OPTION_FP32 (OPTION_MISC_BASE + 4) {"mfp32", no_argument, NULL, OPTION_FP32}, -#define OPTION_GP32 (OPTION_MISC_BASE + 6) +#define OPTION_GP32 (OPTION_MISC_BASE + 5) {"mgp32", no_argument, NULL, OPTION_GP32}, -#define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) +#define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6) {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, -#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8) +#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, -#define OPTION_FP64 (OPTION_MISC_BASE + 9) +#define OPTION_FP64 (OPTION_MISC_BASE + 8) {"mfp64", no_argument, NULL, OPTION_FP64}, -#define OPTION_GP64 (OPTION_MISC_BASE + 10) +#define OPTION_GP64 (OPTION_MISC_BASE + 9) {"mgp64", no_argument, NULL, OPTION_GP64}, -#define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11) -#define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12) +#define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10) +#define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11) {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, /* ELF-specific options. */ #ifdef OBJ_ELF -#define OPTION_ELF_BASE (OPTION_MISC_BASE + 13) +#define OPTION_ELF_BASE (OPTION_MISC_BASE + 12) #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, @@ -10489,22 +10281,12 @@ md_parse_option (int c, char *arg) mips_opts.ase_mips3d = 0; break; - case OPTION_MEMBEDDED_PIC: - mips_pic = EMBEDDED_PIC; - if (USE_GLOBAL_POINTER_OPT && g_switch_seen) - { - as_bad (_("-G may not be used with embedded PIC code")); - return 0; - } - g_switch_value = 0x7fffffff; + case OPTION_FIX_VR4120: + mips_fix_vr4120 = 1; break; - case OPTION_FIX_VR4122: - mips_fix_4122_bugs = 1; - break; - - case OPTION_NO_FIX_VR4122: - mips_fix_4122_bugs = 0; + case OPTION_NO_FIX_VR4120: + mips_fix_vr4120 = 0; break; case OPTION_RELAX_BRANCH: @@ -10554,14 +10336,9 @@ md_parse_option (int c, char *arg) #endif /* OBJ_ELF */ case 'G': - if (! USE_GLOBAL_POINTER_OPT) - { - as_bad (_("-G is not supported for this configuration")); - return 0; - } - else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) + if (mips_pic == SVR4_PIC) { - as_bad (_("-G may not be used with SVR4 or embedded PIC code")); + as_bad (_("-G may not be used with SVR4 PIC code")); return 0; } else @@ -10962,24 +10739,7 @@ mips_frob_file (void) } } -/* When generating embedded PIC code we need to use a special - relocation to represent the difference of two symbols in the .text - section (switch tables use a difference of this sort). See - include/coff/mips.h for details. This macro checks whether this - fixup requires the special reloc. */ -#define SWITCH_TABLE(fixp) \ - ((fixp)->fx_r_type == BFD_RELOC_32 \ - && OUTPUT_FLAVOR != bfd_target_elf_flavour \ - && (fixp)->fx_addsy != NULL \ - && (fixp)->fx_subsy != NULL \ - && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ - && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) - -/* When generating embedded PIC code we must keep all PC relative - relocations, in case the linker has to relax a call. We also need - to keep relocations for switch table entries. - - We may have combined relocations without symbols in the N32/N64 ABI. +/* We may have combined relocations without symbols in the N32/N64 ABI. We have to prevent gas from dropping them. */ int @@ -10995,11 +10755,7 @@ mips_force_relocation (fixS *fixp) || fixp->fx_r_type == BFD_RELOC_LO16)) return 1; - return (mips_pic == EMBEDDED_PIC - && (fixp->fx_pcrel - || SWITCH_TABLE (fixp) - || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S - || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); + return 0; } /* This hook is called before a fix is simplified. We don't really @@ -11039,9 +10795,8 @@ mips_validate_fix (struct fix *fixP, asection *seg) whole function). */ if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 - && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour - || OUTPUT_FLAVOR == bfd_target_elf_flavour) - && mips_pic != EMBEDDED_PIC) + && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour + || OUTPUT_FLAVOR == bfd_target_elf_flavour) || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) && fixP->fx_addsy) { @@ -11106,7 +10861,8 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); /* We are not done if this is a composite relocation to set up gp. */ - if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel + assert (! fixP->fx_pcrel); + if (fixP->fx_addsy == NULL && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB || (fixP->fx_r_type == BFD_RELOC_64 && (previous_fx_r_type == BFD_RELOC_GPREL32 @@ -11147,9 +10903,7 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) case BFD_RELOC_MIPS_CALL_HI16: case BFD_RELOC_MIPS_CALL_LO16: case BFD_RELOC_MIPS16_GPREL: - if (fixP->fx_pcrel) - as_bad_where (fixP->fx_file, fixP->fx_line, - _("Invalid PC relative reloc")); + assert (! fixP->fx_pcrel); /* Nothing needed to do. The value comes from the reloc entry */ break; @@ -11160,44 +10914,10 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) *valP = 0; break; - case BFD_RELOC_PCREL_HI16_S: - /* The addend for this is tricky if it is internal, so we just - do everything here rather than in bfd_install_relocation. */ - if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) - break; - if (fixP->fx_addsy - && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) - { - /* For an external symbol adjust by the address to make it - pcrel_offset. We use the address of the RELLO reloc - which follows this one. */ - *valP += (fixP->fx_next->fx_frag->fr_address - + fixP->fx_next->fx_where); - } - *valP = ((*valP + 0x8000) >> 16) & 0xffff; - if (target_big_endian) - buf += 2; - md_number_to_chars (buf, *valP, 2); - break; - - case BFD_RELOC_PCREL_LO16: - /* The addend for this is tricky if it is internal, so we just - do everything here rather than in bfd_install_relocation. */ - if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) - break; - if (fixP->fx_addsy - && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) - *valP += fixP->fx_frag->fr_address + fixP->fx_where; - if (target_big_endian) - buf += 2; - md_number_to_chars (buf, *valP, 2); - break; - case BFD_RELOC_64: /* This is handled like BFD_RELOC_32, but we output a sign extended value if we are only 32 bits. */ - if (fixP->fx_done - || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) + if (fixP->fx_done) { if (8 <= sizeof (valueT)) md_number_to_chars (buf, *valP, 8); @@ -11221,11 +10941,8 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) case BFD_RELOC_32: /* If we are deleting this reloc entry, we must fill in the value now. This can happen if we have a .word which is not - resolved when it appears but is later defined. We also need - to fill in the value if this is an embedded PIC switch table - entry. */ - if (fixP->fx_done - || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) + resolved when it appears but is later defined. */ + if (fixP->fx_done) md_number_to_chars (buf, *valP, 4); break; @@ -11238,6 +10955,8 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) break; case BFD_RELOC_LO16: + /* FIXME: Now that embedded-PIC is gone, some of this code/comment + may be safe to remove, but if so it's not obvious. */ /* When handling an embedded PIC switch statement, we can wind up deleting a LO16 reloc. See the 'o' case in mips_ip. */ if (fixP->fx_done) @@ -11508,13 +11227,6 @@ s_change_sec (int sec) { segT seg; - /* When generating embedded PIC code, we only use the .text, .lit8, - .sdata and .sbss sections. We change the .data and .rdata - pseudo-ops to use .sdata. */ - if (mips_pic == EMBEDDED_PIC - && (sec == 'd' || sec == 'r')) - sec = 's'; - #ifdef OBJ_ELF /* The ELF backend needs to know that we are changing sections, so that .previous works correctly. We could do something like check @@ -11540,52 +11252,30 @@ s_change_sec (int sec) break; case 'r': - if (USE_GLOBAL_POINTER_OPT) - { - seg = subseg_new (RDATA_SECTION_NAME, - (subsegT) get_absolute_expression ()); - if (OUTPUT_FLAVOR == bfd_target_elf_flavour) - { - bfd_set_section_flags (stdoutput, seg, - (SEC_ALLOC - | SEC_LOAD - | SEC_READONLY - | SEC_RELOC - | SEC_DATA)); - if (strcmp (TARGET_OS, "elf") != 0) - record_alignment (seg, 4); - } - demand_empty_rest_of_line (); - } - else + seg = subseg_new (RDATA_SECTION_NAME, + (subsegT) get_absolute_expression ()); + if (OUTPUT_FLAVOR == bfd_target_elf_flavour) { - as_bad (_("No read only data section in this object file format")); - demand_empty_rest_of_line (); - return; + bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD + | SEC_READONLY | SEC_RELOC + | SEC_DATA)); + if (strcmp (TARGET_OS, "elf") != 0) + record_alignment (seg, 4); } + demand_empty_rest_of_line (); break; case 's': - if (USE_GLOBAL_POINTER_OPT) - { - seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); - if (OUTPUT_FLAVOR == bfd_target_elf_flavour) - { - bfd_set_section_flags (stdoutput, seg, - SEC_ALLOC | SEC_LOAD | SEC_RELOC - | SEC_DATA); - if (strcmp (TARGET_OS, "elf") != 0) - record_alignment (seg, 4); - } - demand_empty_rest_of_line (); - break; - } - else + seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); + if (OUTPUT_FLAVOR == bfd_target_elf_flavour) { - as_bad (_("Global pointers not supported; recompile -G 0")); - demand_empty_rest_of_line (); - return; + bfd_set_section_flags (stdoutput, seg, + SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); + if (strcmp (TARGET_OS, "elf") != 0) + record_alignment (seg, 4); } + demand_empty_rest_of_line (); + break; } auto_align = 1; @@ -11781,7 +11471,7 @@ s_option (int x ATTRIBUTE_UNUSED) else as_bad (_(".option pic%d not supported"), i); - if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) + if (mips_pic == SVR4_PIC) { if (g_switch_seen && g_switch_value != 0) as_warn (_("-G may not be used with SVR4 PIC code")); @@ -11891,34 +11581,11 @@ s_mipsset (int x ATTRIBUTE_UNUSED) /* Permit the user to change the ISA and architecture on the fly. Needless to say, misuse can cause serious problems. */ - if (strcmp (name, "mips0") == 0) + if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) { reset = 1; mips_opts.isa = file_mips_isa; - } - else if (strcmp (name, "mips1") == 0) - mips_opts.isa = ISA_MIPS1; - else if (strcmp (name, "mips2") == 0) - mips_opts.isa = ISA_MIPS2; - else if (strcmp (name, "mips3") == 0) - mips_opts.isa = ISA_MIPS3; - else if (strcmp (name, "mips4") == 0) - mips_opts.isa = ISA_MIPS4; - else if (strcmp (name, "mips5") == 0) - mips_opts.isa = ISA_MIPS5; - else if (strcmp (name, "mips32") == 0) - mips_opts.isa = ISA_MIPS32; - else if (strcmp (name, "mips32r2") == 0) - mips_opts.isa = ISA_MIPS32R2; - else if (strcmp (name, "mips64") == 0) - mips_opts.isa = ISA_MIPS64; - else if (strcmp (name, "mips64r2") == 0) - mips_opts.isa = ISA_MIPS64R2; - else if (strcmp (name, "arch=default") == 0) - { - reset = 1; mips_opts.arch = file_mips_arch; - mips_opts.isa = file_mips_isa; } else if (strncmp (name, "arch=", 5) == 0) { @@ -11933,8 +11600,21 @@ s_mipsset (int x ATTRIBUTE_UNUSED) mips_opts.isa = p->isa; } } + else if (strncmp (name, "mips", 4) == 0) + { + const struct mips_cpu_info *p; + + p = mips_parse_cpu("internal use", name); + if (!p) + as_bad (_("unknown ISA level %s"), name + 4); + else + { + mips_opts.arch = p->cpu; + mips_opts.isa = p->isa; + } + } else - as_bad (_("unknown ISA level %s"), name + 4); + as_bad (_("unknown ISA or architecture %s"), name); switch (mips_opts.isa) { @@ -12022,12 +11702,11 @@ s_abicalls (int ignore ATTRIBUTE_UNUSED) { mips_pic = SVR4_PIC; mips_abicalls = TRUE; - if (USE_GLOBAL_POINTER_OPT) - { - if (g_switch_seen && g_switch_value != 0) - as_warn (_("-G may not be used with SVR4 PIC code")); - g_switch_value = 0; - } + + if (g_switch_seen && g_switch_value != 0) + as_warn (_("-G may not be used with SVR4 PIC code")); + g_switch_value = 0; + bfd_set_gp_size (stdoutput, 0); demand_empty_rest_of_line (); } @@ -12584,7 +12263,7 @@ nopic_need_relax (symbolS *sym, int before_relaxing) if (sym == 0) return 0; - if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) + if (g_switch_value > 0) { const char *symname; int change; @@ -12691,9 +12370,7 @@ pic_need_relax (symbolS *sym, asection *segtype) #ifdef OBJ_ELF /* A global or weak symbol is treated as external. */ && (OUTPUT_FLAVOR != bfd_target_elf_flavour - || (! S_IS_WEAK (sym) - && (! S_IS_EXTERNAL (sym) - || mips_pic == EMBEDDED_PIC))) + || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym))) #endif ); } @@ -13046,60 +12723,8 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; - if (mips_pic == EMBEDDED_PIC - && SWITCH_TABLE (fixp)) - { - /* For a switch table entry we use a special reloc. The addend - is actually the difference between the reloc address and the - subtrahend. */ - reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); - if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) - as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); - fixp->fx_r_type = BFD_RELOC_GPREL32; - } - else if (fixp->fx_pcrel) - { - bfd_vma pcrel_address; - - /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high - high-part relocs is the address of the low-part reloc. */ - if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) - { - assert (fixp->fx_next != NULL - && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); - pcrel_address = (fixp->fx_next->fx_where - + fixp->fx_next->fx_frag->fr_address); - } - else - pcrel_address = reloc->address; - - if (OUTPUT_FLAVOR == bfd_target_elf_flavour) - { - /* At this point, fx_addnumber is "symbol offset - pcrel_address". - Relocations want only the symbol offset. */ - reloc->addend = fixp->fx_addnumber + pcrel_address; - } - else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16 - || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) - { - /* We use a special addend for an internal RELLO or RELHI reloc. */ - if (symbol_section_p (fixp->fx_addsy)) - reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy); - else - reloc->addend = fixp->fx_addnumber + pcrel_address; - } - else - { - if (OUTPUT_FLAVOR != bfd_target_aout_flavour) - /* A gruesome hack which is a result of the gruesome gas reloc - handling. */ - reloc->addend = pcrel_address; - else - reloc->addend = -pcrel_address; - } - } - else - reloc->addend = fixp->fx_addnumber; + assert (! fixp->fx_pcrel); + reloc->addend = fixp->fx_addnumber; /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable entry to be used in the relocation's section offset. */ @@ -13109,49 +12734,16 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) reloc->addend = 0; } - /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that - fixup_segment converted a non-PC relative reloc into a PC - relative reloc. In such a case, we need to convert the reloc - code. */ code = fixp->fx_r_type; - if (fixp->fx_pcrel) - { - switch (code) - { - case BFD_RELOC_8: - code = BFD_RELOC_8_PCREL; - break; - case BFD_RELOC_16: - code = BFD_RELOC_16_PCREL; - break; - case BFD_RELOC_32: - code = BFD_RELOC_32_PCREL; - break; - case BFD_RELOC_64: - code = BFD_RELOC_64_PCREL; - break; - case BFD_RELOC_8_PCREL: - case BFD_RELOC_16_PCREL: - case BFD_RELOC_32_PCREL: - case BFD_RELOC_64_PCREL: - case BFD_RELOC_16_PCREL_S2: - case BFD_RELOC_PCREL_HI16_S: - case BFD_RELOC_PCREL_LO16: - break; - default: - as_bad_where (fixp->fx_file, fixp->fx_line, - _("Cannot make %s relocation PC relative"), - bfd_get_reloc_code_name (code)); - } - } - /* To support a PC relative reloc when generating embedded PIC code - for ECOFF, we use a Cygnus extension. We check for that here to - make sure that we don't let such a reloc escape normally. */ + /* To support a PC relative reloc, we used a Cygnus extension. + We check for that here to make sure that we don't let such a + reloc escape normally. (FIXME: This was formerly used by + embedded-PIC support, but is now used by branch handling in + general. That probably should be fixed.) */ if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour || OUTPUT_FLAVOR == bfd_target_elf_flavour) - && code == BFD_RELOC_16_PCREL_S2 - && mips_pic != EMBEDDED_PIC) + && code == BFD_RELOC_16_PCREL_S2) reloc->howto = NULL; else reloc->howto = bfd_reloc_type_lookup (stdoutput, code); @@ -14331,7 +13923,6 @@ md_show_usage (FILE *stream) fprintf (stream, _("\ MIPS options:\n\ --membedded-pic generate embedded position independent code\n\ -EB generate big endian output\n\ -EL generate little endian output\n\ -g, -g2 do not remove unneeded NOPs or swap branches\n\ @@ -14373,6 +13964,7 @@ MIPS options:\n\ -mips16 generate mips16 instructions\n\ -no-mips16 do not generate mips16 instructions\n")); fprintf (stream, _("\ +-mfix-vr4120 work around certain VR4120 errata\n\ -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ -O0 remove unneeded NOPs, do not swap branches\n\ @@ -14425,10 +14017,6 @@ mips_dwarf2_addr_size (void) { if (mips_abi == N64_ABI) return 8; - /* GCC for 64-bit targets turns on mlong64 giving - us 64-bit addresses. */ - else if (mips_abi == EABI_ABI && !file_mips_gp32) - return 8; else return 4; } |