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-@c Copyright (C) 1996, 1998, 1999 Free Software Foundation, Inc.
-@c This is part of the GAS manual.
-@c For copying conditions, see the file as.texinfo.
-
-@ifset GENERIC
-@page
-@node ARM-Dependent
-@chapter ARM Dependent Features
-@end ifset
-
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter ARM Dependent Features
-@end ifclear
-
-@cindex ARM support
-@cindex Thumb support
-@menu
-* ARM Options::              Options
-* ARM Syntax::               Syntax
-* ARM Floating Point::       Floating Point
-* ARM Directives::           ARM Machine Directives
-* ARM Opcodes::              Opcodes
-@end menu
-
-@node ARM Options
-@section Options
-@cindex ARM options (none)
-@cindex options for ARM (none)
-@table @code
-@cindex @code{-marm} command line option, ARM
-@item -marm [@var{2}|@var{250}|@var{3}|@var{6}|@var{60}|@var{600}|@var{610}|@var{620}|@var{7}|@var{7m}|@var{7d}|@var{7dm}|@var{7di}|@var{7dmi}|@var{70}|@var{700}|@var{700i}|@var{710}|@var{710c}|@var{7100}|@var{7500}|@var{7500fe}|@var{7tdmi}|@var{8}|@var{810}|@var{9}|@var{9tdmi}|@var{920}|@var{strongarm}|@var{strongarm110}|@var{strongarm1100}]
-This option specifies the target processor.  The assembler will issue an
-error message if an attempt is made to assemble an instruction which
-will not execute on the target processor.
-@cindex @code{-marmv} command line option, ARM
-@item -marmv [@var{2}|@var{2a}|@var{3}|@var{3m}|@var{4}|@var{4t}|@var{5}|@var{5t}]
-This option specifies the target architecture.  The assembler will issue
-an error message if an attempt is made to assemble an instruction which
-will not execute on the target architecture.
-@cindex @code{-mthumb} command line option, ARM
-@item -mthumb
-This option specifies that only Thumb instructions should be assembled.
-@cindex @code{-mall} command line option, ARM
-@item -mall
-This option specifies that any Arm or Thumb instruction should be assembled.
-@cindex @code{-mfpa} command line option, ARM
-@item -mfpa [@var{10}|@var{11}]
-This option specifies the floating point architecture in use on the
-target processor. 
-@cindex @code{-mfpe-old} command line option, ARM
-@item -mfpe-old
-Do not allow the assemble of floating point multiple instructions.
-@cindex @code{-mno-fpu} command line option, ARM
-@item -mno-fpu
-Do not allow the assembly of any floating point instructions.
-@cindex @code{-mthumb-interwork} command line option, ARM
-@item -mthumb-interwork
-This option specifies that the output generated by the assembler should
-be marked as supporting interworking.
-@cindex @code{-mapcs} command line option, ARM
-@item -mapcs [@var{26}|@var{32}]
-This option specifies that the output generated by the assembler should
-be marked as supporting the indicated version of the Arm Procedure.
-Calling Standard.
-@item -mapcs-float
-This indicates the the floating point variant of the APCS should be
-used.  In this variant floating point arguments are passed in FP
-registers ratehr than integer registers.
-@item -mapcs-reentrant
-This indicates that the reentrant variant of the APCS should be used.
-This variant supports position independent code.
-@cindex @code{-EB} command line option, ARM
-@item -EB
-This option specifies that the output generated by the assembler should
-be marked as being encoded for a big-endian processor.
-@cindex @code{-EL} command line option, ARM
-@item -EL
-This option specifies that the output generated by the assembler should
-be marked as being encoded for a little-endian processor.
-@cindex @code{-k} command line option, ARM
-@cindex PIC code generation for ARM
-@item -k
-This option enables the generation of PIC (position independent code).
-@item -moabi
-This indicates that the code should be assembled using the old ARM ELF
-conventions, based on a beta release release of the ARM-ELF
-specifications, rather than the default conventions which are based on
-the final release of the ARM-ELF specifications.
-@end table
-
-
-@node ARM Syntax
-@section Syntax
-@menu
-* ARM-Chars::                Special Characters
-* ARM-Regs::                 Register Names
-@end menu
-
-@node ARM-Chars
-@subsection Special Characters
-
-@cindex line comment character, ARM
-@cindex ARM line comment character
-The presence of a @samp{#} and @samp{@@} on a line indicates the start of
-a comment that extends to the end of the current line.
-
-@cindex identifiers, ARM
-@cindex ARM identifiers
-*TODO* Explain about /data modifier on symbols.
-
-@node ARM-Regs
-@subsection Register Names
-
-@cindex ARM register names
-@cindex register names, ARM
-*TODO* Explain about ARM register naming, and the predefined names.
-
-@node ARM Floating Point
-@section Floating Point
-
-@cindex floating point, ARM (@sc{ieee})
-@cindex ARM floating point (@sc{ieee})
-The ARM family uses @sc{ieee} floating-point numbers.
-
-
-
-@node ARM Directives
-@section ARM Machine Directives
-
-@cindex machine directives, ARM
-@cindex ARM machine directives
-@table @code
-
-@cindex @code{req} directive, ARM
-@item @var{name} .req @var{register name}
-This creates an alias for @var{register name} called @var{name}.  For
-example:
-
-@smallexample
-        foo .req r0
-@end smallexample
-
-@cindex @code{code} directive, ARM
-@item .code [@var{16}|@var{32}]
-This directive selects the instruction set being generated. The value 16
-selects Thumb, with the value 32 selecting ARM.
-
-@cindex @code{thumb} directive, ARM
-@item .thumb
-This performs the same action as @var{.code 16}.
-
-@cindex @code{arm} directive, ARM
-@item .arm
-This performs the same action as @var{.code 32}.
-
-@cindex @code{force_thumb} directive, ARM
-@item .force_thumb
-This directive forces the selection of Thumb instructions, even if the
-target processor does not support those instructions
-
-@cindex @code{thumb_func} directive, ARM
-@item .thumb_func
-This directive specifies that the following symbol is the name of a
-Thumb encoded function.  This information is necessary in order to allow
-the assembler and linker to generate correct code for interworking
-between Arm and Thumb instructions and should be used even if
-interworking is not going to be performed.
-
-@cindex @code{thumb_set} directive, ARM
-@item .thumb_set
-This performs the equivalent of a @code{.set} directive in that it
-creates a symbol which is an alias for another symbol (possibly not yet
-defined).  This directive also has the added property in that it marks
-the aliased symbol as being a thumb function entry point, in the same
-way that the @code{.thumb_func} directive does.
-
-@cindex @code{.ltorg} directive, ARM
-@item .ltorg
-This directive causes the current contents of the literal pool to be
-dumped into the current section (which is assumed to be the .text
-section) at the current location (aligned to a word boundary).
-
-@cindex @code{.pool} directive, ARM
-@item .pool
-This is a synonym for .ltorg.
-
-@end table
-
-@node ARM Opcodes
-@section Opcodes
-
-@cindex ARM opcodes
-@cindex opcodes for ARM
-@code{@value{AS}} implements all the standard ARM opcodes.  It also
-implements several pseudo opcodes, including several synthetic load
-instructions. 
-
-@table @code
-
-@cindex @code{NOP} pseudo op, ARM
-@item NOP
-@smallexample
-  nop
-@end smallexample
-
-This pseudo op will always evaluate to a legal ARM instruction that does
-nothing.  Currently it will evaluate to MOV r0, r0.
-
-@cindex @code{LDR reg,=<label>} pseudo op, ARM
-@item LDR 
-@smallexample
-  ldr <register> , = <expression>
-@end smallexample
-
-If expression evaluates to a numeric constant then a MOV or MVN
-instruction will be used in place of the LDR instruction, if the
-constant can be generated by either of these instructions.  Otherwise
-the constant will be placed into the nearest literal pool (if it not
-already there) and a PC relative LDR instruction will be generated.
-
-@cindex @code{ADR reg,<label>} pseudo op, ARM
-@item ADR
-@smallexample
-  adr <register> <label>
-@end smallexample
-
-This instruction will load the address of @var{label} into the indicated
-register.  The instruction will evaluate to a PC relative ADD or SUB
-instruction depending upon where the label is located.  If the label is
-out of range, or if it is not defined in the same file (and section) as
-the ADR instruction, then an error will be generated.  This instruction
-will not make use of the literal pool.
-
-@cindex @code{ADRL reg,<label>} pseudo op, ARM
-@item ADRL 
-@smallexample
-  adrl <register> <label>
-@end smallexample
-
-This instruction will load the address of @var{label} into the indicated
-register.  The instruction will evaluate to one or two a PC relative ADD
-or SUB instructions depending upon where the label is located.  If a
-second instruction is not needed a NOP instruction will be generated in
-its place, so that this instruction is always 8 bytes long.
-
-If the label is out of range, or if it is not defined in the same file
-(and section) as the ADRL instruction, then an error will be generated.
-This instruction will not make use of the literal pool.
-
-@end table
-
-For information on the ARM or Thumb instruction sets, see @cite{ARM
-Software Development Toolkit Reference Manual}, Advanced RISC Machines
-Ltd.
-