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path: root/gas/config/tc-i386.c
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* x86: Check invalid XMM register in AVX512 gathersH.J. Lu2017-10-261-1/+2
* i386: Support .code64 directive only with 64-bit bfdH.J. Lu2017-10-241-0/+2
* Enable Intel AVX512_BITALG instructions.Igor Tsimbalist2017-10-231-0/+3
* Enable Intel AVX512_VNNI instructions.Igor Tsimbalist2017-10-231-0/+3
* Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist2017-10-231-0/+2
* Enable Intel VAES instructions.Igor Tsimbalist2017-10-231-0/+2
* Enable Intel GFNI instructions.Igor Tsimbalist2017-10-231-0/+2
* Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist2017-10-231-0/+20
* x86: Remove restriction on NOTRACK prefix positionH.J. Lu2017-09-091-40/+19
* x86: CET v2.0: Update NOTRACK prefixH.J. Lu2017-06-211-7/+2
* x86: Add NOTRACK prefix supportH.J. Lu2017-05-221-17/+58
* X86: Add pseudo prefixes to control encodingH.J. Lu2017-03-091-44/+114
* Add support for Intel CET instructionsH.J. Lu2017-03-061-0/+2
* Fix spelling mistakes and typos in the GAS sources.Nick Clifton2017-01-231-8/+8
* Fix potential array overrun in x86 assembler.Nick Clifton2017-01-201-1/+1
* Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist2017-01-121-0/+3
* Update year range in copyright notice of all files.Alan Modra2017-01-021-1/+1
* Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist2016-11-021-0/+3
* Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist2016-11-021-0/+22
* X86: Remove pcommit instructionH.J. Lu2016-10-211-2/+0
* -Wimplicit-fallthrough warning fixesAlan Modra2016-10-061-0/+35
* Allow PROCESSOR_IAMCU for Intel MCUH.J. Lu2016-09-081-1/+1
* X86: Allow additional ISAs for IAMCU in assemblerH.J. Lu2016-09-071-21/+2
* X86: Add ptwrite instructionH.J. Lu2016-08-241-0/+2
* x86: fix register check in check_qword_reg()Jan Beulich2016-07-051-1/+1
* x86-64/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich2016-07-011-0/+17
* x86/MPX: fix address size handlingJan Beulich2016-07-011-4/+9
* x86/Intel: don't accept bogus instructionsJan Beulich2016-07-011-5/+27
* x86/Intel: fix operand checking for MOVSDJan Beulich2016-07-011-1/+53
* Add .noavx512XX directives to x86 assemblerH.J. Lu2016-05-291-0/+9
* Update x86 CPU_XXX_FLAGS handlingH.J. Lu2016-05-271-5/+20
* Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu2016-05-271-7/+4
* Correct CpuMax in i386-opc.hH.J. Lu2016-05-271-8/+11
* Don't clear cpu64 nor cpuno64H.J. Lu2016-05-271-2/+0
* Require another match for AVX512VLH.J. Lu2016-05-251-0/+15
* Reimplement .no87/.nommx/.nosse/.noavx directivesH.J. Lu2016-05-251-163/+253
* Preserve addend for R_386_GOT32 and R_X86_64_GOT32H.J. Lu2016-05-201-5/+0
* use XNEW and related macros moreTrevor Saunders2016-05-131-7/+7
* Enable Intel RDPID instruction.Alexander Fomin2016-05-101-0/+2
* Don't use vec_disp8 encoding with the .d32 suffixH.J. Lu2016-04-041-1/+3
* Constify moreAlan Modra2016-04-011-2/+2
* make md_parse_option () take a const char *Trevor Saunders2016-03-291-1/+1
* tc-i386.c: store encoded instructions in unsigned char[]Trevor Saunders2016-03-201-33/+33
* [i386] Check RegVRex in register_numberH.J. Lu2016-02-201-0/+3
* Add -mrelax-relocations= to x86 assemblerH.J. Lu2016-02-031-3/+27
* Add option -mfence-as-lock-add=[no|yes].Andrew Senkevich2016-01-291-0/+35
* Rename OPTION_OMIT_LOCK_PREFIX to OPTION_MOMIT_LOCK_PREFIXH.J. Lu2016-01-251-3/+3
* Copyright update for binutilsAlan Modra2016-01-011-1/+1
* Process 64-bit imm/disp only for 64-bit BFDH.J. Lu2015-12-181-0/+6
* Implement Intel OSPKE instructionsH.J. Lu2015-12-091-0/+2
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