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path: root/include/opcode/mips.h
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* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* MIPS/opcodes: Properly handle ISA exclusionMaciej W. Rozycki2021-05-291-19/+18
* MIPS/opcodes: Factor out ISA matching against flagsMaciej W. Rozycki2021-05-291-4/+21
* MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki2021-05-291-2/+9
* MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki2021-05-291-2/+1
* Use bool in includeAlan Modra2021-03-311-17/+17
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
* Add load-link, store-conditional paired EVA instructionsFaraz Shahbazker2019-05-061-0/+5
* [MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett2019-04-261-0/+4
* MIPS/include: opcode/mips.h: Update stale comment for CODE20 operandMaciej W. Rozycki2019-04-251-2/+2
* Update year range in copyright notice of binutils filesAlan Modra2019-01-011-1/+1
* [MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu2018-08-291-0/+1
* [MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu2018-08-291-0/+1
* [MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu2018-08-291-7/+2
* [MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu2018-08-291-0/+2
* [MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu2018-08-291-0/+2
* [MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu2018-08-291-0/+2
* MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu2018-07-201-0/+2
* MIPS: Add Global INValidate ASE supportFaraz Shahbazker2018-06-141-1/+6
* MIPS: Add CRC ASE supportScott Egerton2018-06-131-0/+3
* MIPS16/opcodes: Free up `M' operand codeMaciej W. Rozycki2018-02-201-3/+2
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-1/+1
* MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki2017-06-301-0/+3
* MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki2017-06-281-5/+16
* MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki2017-05-151-5/+34
* Update year range in copyright notice of all files.Alan Modra2017-01-021-1/+1
* MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki2016-12-231-2/+8
* MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki2016-12-231-5/+5
* MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki2016-12-231-0/+4
* MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki2016-12-201-0/+8
* MIPS16: Remove unused `>' operand codeMaciej W. Rozycki2016-12-091-2/+1
* MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASKMaciej W. Rozycki2016-12-071-1/+1
* MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3Maciej W. Rozycki2016-12-071-0/+1
* add more extern CTrevor Saunders2016-06-011-0/+8
* Add MIPS32 DSPr3 support.Matthew Fortune2016-05-111-0/+1
* MIPS/include: opcode/mips.h: Add a summary of MIPS16 operand codesMaciej W. Rozycki2016-01-061-0/+6
* Copyright update for binutilsAlan Modra2016-01-011-1/+1
* ChangeLog rotatation and copyright year updateAlan Modra2015-01-021-1/+1
* MIPS: Add Octeon 3 supportNaveen H.S2014-10-311-0/+5
* Add support for MIPS R6.Andrew Bennett2014-09-151-8/+93
* MIPS: Make the CODE10 operand code consistent between ISAsMaciej W. Rozycki2014-08-261-3/+4
* [MIPS] Rename COPROC related macrosMatthew Fortune2014-07-291-4/+4
* Add MIPS r3 and r5 support.Andrew Bennett2014-05-071-9/+30
* include/opcode/Richard Sandiford2014-05-011-10/+27
* Add support for the MIPS eXtended Physical Address (XPA) ASE.Andrew Bennett2014-04-231-0/+2
* Update copyright yearsAlan Modra2014-03-051-3/+1
* Range of element index is too large on MIPS MSA element selection instructions.Andrew Bennett2013-12-161-8/+8
* 2013-11-11 Catherine Moore <clm@codesourcery.com>Catherine Moore2013-11-111-2/+2
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