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path: root/include/opcode/riscv.h
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* RISC-V: Support XVentanaCondOps extensionPhilipp Tomsich2023-04-261-0/+1
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
* RISC-V: Add T-Head Int vendor extensionChristoph Müllner2022-11-171-0/+1
* RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner2022-11-171-0/+1
* RISC-V: Move certain arrays to riscv-opc.cTsukasa OI2022-10-141-11/+2
* RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI2022-10-041-0/+2
* RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu2022-10-041-7/+7
* RISC-V/gas: allow generating up to 176-bit instructions with .insnJan Beulich2022-10-041-0/+3
* RISC-V: Add Zawrs ISA extension supportChristoph Müllner2022-09-231-0/+1
* RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner2022-09-221-0/+1
* RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner2022-09-221-0/+1
* RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner2022-09-221-0/+1
* RISC-V: Add T-Head MAC vendor extensionChristoph Müllner2022-09-221-0/+1
* RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner2022-09-221-0/+1
* RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner2022-09-221-0/+3
* RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner2022-09-221-0/+17
* RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner2022-09-221-0/+1
* RISC-V: Add T-Head CMO vendor extensionChristoph Müllner2022-09-221-0/+1
* RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI2022-08-301-0/+1
* RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI2022-07-071-3/+4
* RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu2022-06-221-0/+1
* RISC-V: Add zhinx extension supports.jiawei2022-05-301-2/+3
* RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu2022-05-171-0/+5
* RISC-V: Cache management instructionsTsukasa OI2022-03-181-0/+2
* RISC-V: Prefetch hint instructions and operand setTsukasa OI2022-03-181-0/+1
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu2021-12-161-0/+1
* RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu2021-11-301-2/+0
* RISC-V: Add instructions and operand set for z[fdq]inxjiawei2021-11-181-0/+3
* RISC-V: Support rvv extension with released version 1.0.Nelson Chu2021-11-171-0/+58
* RISC-V: Scalar crypto instructions and operand set.jiawei2021-11-161-0/+18
* RISC-V: Add support for Zbs instructionsPhilipp Tomsich2021-10-071-0/+1
* RISC-V: PR27916, Support mapping symbols.Nelson Chu2021-08-301-0/+7
* RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen2021-03-161-0/+3
* RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu2021-02-191-64/+71
* RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu2021-02-181-69/+0
* RISC-V: PR27348, Remove the obsolete OP_*CUSTOM_IMM.Nelson Chu2021-02-051-2/+0
* RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.Nelson Chu2021-02-041-4/+0
* RISC-V: Indent and GNU coding standards tidy, also aligned the code.Nelson Chu2021-01-151-44/+51
* RISC-V: Comments tidy and improvement.Nelson Chu2021-01-151-23/+9
* RISC-V: Add pause hint instruction.Philipp Tomsich2021-01-071-0/+1
* RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).Claire Xenia Wolf2021-01-071-1/+6
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu2020-12-101-0/+4
* RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu2020-12-101-2/+4
* RISC-V: Support to add implicit extensions for G.Nelson Chu2020-12-011-0/+2
* RISC-V: Improve the version parsing for arch string.Nelson Chu2020-12-011-2/+2
* PR26493 UBSAN: elfnn-riscv.c left shift of negative valueAlan Modra2020-08-311-4/+4
* RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu2020-06-301-0/+1
* RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu2020-06-221-4/+0
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