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* Allow the --visualize-jumps feature to work with the AVR disassembler.Marcus Nilsson2021-12-021-0/+5
* opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess2021-11-261-0/+9
* Fix building the AArch64 assembler and disassembler when assertions are disab...Nick Clifton2021-11-251-0/+7
* Updated French translation for the opcodes directory.Nick Clifton2021-11-251-0/+4
* opcodes: Fix RPATH not being set for dynamic libbfd dependencyMaciej W. Rozycki2021-10-271-0/+8
* configure: regenerate in all projects that use libtool.m4Nick Alcock2021-09-271-0/+4
* PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5Peter Bergner2021-09-251-0/+5
* riscv: print .2byte or .4byte before an unknown instruction encodingAndrew Burgess2021-09-201-0/+6
* Fix the V850 assembler's generation of relocations for the st.b instruction.Nick Clifton2021-09-021-0/+6
* opcodes: Fix the auxiliary register numbers for ARC HSShahab Vahedi2021-08-171-0/+4
* Updated Serbian and Russian translations for various sub-directoriesNick Clifton2021-08-101-0/+4
* Correct gs264e bfd_mach in mips_arch_choices.Chenghua Xu2021-07-271-0/+4
* Add changelog entries for last commitAndreas Krebbel2021-07-071-0/+4
* Update version number and regenerate filesNick Clifton2021-07-031-0/+5
* Add markers for 2.37 branchNick Clifton2021-07-031-0/+4
* Re: Fix minor NDS32 renaming snafuAlan Modra2021-07-021-0/+9
* cgen: split GUILE setting outMike Frysinger2021-07-011-0/+6
* opcodes: constify & local meps macrosMike Frysinger2021-07-011-0/+7
* opcodes: cleanup nds32 variablesMike Frysinger2021-07-011-0/+17
* opcodes: constify & localize z80 opcodesMike Frysinger2021-07-011-0/+5
* opcodes: constify & scope microblaze opcodesMike Frysinger2021-07-011-0/+12
* opcodes: constify aarch64_opcode_tablesMike Frysinger2021-07-011-1/+6
* opcodes: make use of __builtin_popcount when availableAndrew Burgess2021-06-221-0/+5
* picojava assembler and disassembler fixesAlan Modra2021-06-221-0/+5
* ubsan: vax: pointer overflowAlan Modra2021-06-191-0/+4
* Fix another strncpy warningAlan Modra2021-06-191-0/+5
* powerpc: move cell "or rx,rx,rx" hintsAlan Modra2021-06-171-0/+5
* PR1202, mcore disassembler: wrong address looptAlan Modra2021-06-031-0/+6
* arc: Construct disassembler options dynamicallyShahab Vahedi2021-06-021-0/+8
* PowerPC table driven -Mraw disassemblyAlan Modra2021-05-291-0/+15
* MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructionsMaciej W. Rozycki2021-05-291-0/+5
* MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki2021-05-291-0/+10
* MIPS/opcodes: Remove DMFC3 and DMTC3 instructionsMaciej W. Rozycki2021-05-291-0/+5
* MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki2021-05-291-0/+5
* MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki2021-05-291-0/+10
* MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki2021-05-291-0/+14
* MIPS/opcodes: Add TX39 CP0 register namesMaciej W. Rozycki2021-05-291-0/+6
* MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki2021-05-291-0/+6
* microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1Maciej W. Rozycki2021-05-291-0/+5
* PowerPC: Add new xxmr and xxlnot extended mnemonicsPeter Bergner2021-05-271-0/+4
* Regen cris filesAlan Modra2021-05-251-0/+7
* opcodes: cris: move desc & opc files from sim/Mike Frysinger2021-05-241-0/+11
* RISC-V: PR27814, Objdump crashes when disassembling a non-ELF RISC-V binary.Job Noorman2021-05-181-0/+6
* arm: Fix bugs with MVE vmov from two GPRs to vector lanesAlex Coplan2021-05-171-0/+9
* Fix an illegal memory access when attempting to disassemble a corrupt TIC30 b...Nick Clifton2021-05-111-0/+6
* or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha()Stafford Horne2021-05-061-0/+5
* opcodes: xtensa: support branch visualizationMax Filippov2021-05-011-0/+5
* x86: optimize LEAJan Beulich2021-04-261-0/+5
* opcodes: xtensa: display loaded literal valueMax Filippov2021-04-231-0/+5
* opcodes: xtensa: improve literal outputMax Filippov2021-04-231-0/+5
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