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* Correct check for endiannessMichael Eager2017-06-022-1/+5
* Refactor disassembler selectionYao Qi2017-05-242-1/+9
* Fix ldn/stn multiple instructions. Fix testcases with unaligned data.Jim Wilson2017-04-2214-202/+454
* Add support for fcvtl and fcvtl2.Jim Wilson2017-04-084-0/+112
* Support the fcmXX zero instructions.Jim Wilson2017-04-084-0/+232
* Fix bug with cmn/adds where C flag was incorrectly set.Jim Wilson2017-03-254-1/+27
* Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.Jim Wilson2017-03-035-9/+89
* Add missing smov support, and clean up existing umov support.Jim Wilson2017-02-254-75/+227
* Add missing cnt (popcount) instruction support.Jim Wilson2017-02-254-0/+94
* Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.Jim Wilson2017-02-198-36/+157
* Add self to aarch64 maintainers. Fix mla instruction.Jim Wilson2017-02-146-49/+128
* Fix bit/bif instructions.Jim Wilson2017-02-144-10/+107
* Add ldn/stn single support, fix ldnr support.Jim Wilson2017-02-146-269/+698
* sim: use ARRAY_SIZE instead of ad-hoc sizeof calculationsMike Frysinger2017-02-1339-62/+141
* Add support for cmtst.Jim Wilson2017-01-234-0/+113
* Fixes for addv and xtn2 instructions.Jim Wilson2017-01-175-31/+158
* Fix problems with the implementation of the uzp1 and uzp2 instructions.Jim Wilson2017-01-094-17/+273
* Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.Jim Wilson2017-01-049-33/+618
* update copyright year range in GDB filesJoel Brobecker2017-01-01576-576/+576
* Fix bugs with float compare and Inf operands.Jim Wilson2016-12-214-0/+184
* MAINTAINERS: Add myself as a MIPS maintainerMaciej W. Rozycki2016-12-142-0/+6
* Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.Jim Wilson2016-12-137-45/+309
* Fix bugs with tbnz/tbz instructions.users/ARM/embedded-binutils-master-2016q4Jim Wilson2016-12-032-3/+8
* Fix typo in ChangeLog entry.Jim Wilson2016-12-011-1/+1
* Fix bug with FP stur instructions.Jim Wilson2016-12-012-6/+11
* sim: mips: add PR info to ChangeLogMike Frysinger2016-11-121-0/+2
* sim: mips: fix dv-tx3904cpu build errorMike Frysinger2016-11-112-0/+10
* sim: mips: fix builds for r3900 cpus due to missing check_u64Mike Frysinger2016-11-112-0/+5
* sim: avr: move changelog entries to subdirMike Frysinger2016-10-182-7/+7
* sim: m68hc11: use standard STATIC_INLINE helperMike Frysinger2016-08-162-25/+34
* sim: unify symbol table handlingMike Frysinger2016-08-1517-170/+164
* sim: m68hc11: standardize sim_cpu namingMike Frysinger2016-08-1310-347/+366
* sim: m68hc11: fix up various prototype related warningsMike Frysinger2016-08-138-12/+29
* sim: cgen: constify mode_namesMike Frysinger2016-08-133-2/+7
* sim: cgen: drop unused argv/envp definitionsMike Frysinger2016-08-132-8/+5
* sim: bfin: split out common mach/model defines into arch.h [PR sim/20438]Mike Frysinger2016-08-134-26/+55
* Undo the previous change to the aarch64 sim - exporting aarch64_step() - and ...Nick Clifton2016-08-123-9/+19
* Export the single step function from the AArch64 simulator.Nick Clifton2016-08-114-9/+19
* Wean gdb and sim off private libbfd.h headerAlan Modra2016-07-276-7/+18
* Fix typo fsqrt -> sqrtf.Nick Clifton2016-07-211-1/+1
* Use fsqrt() to calculate float (rather than double) square root.Nick Clifton2016-07-212-1/+5
* Update PC when simulate break instruction.Denis Chertykov2016-07-192-2/+8
* Small improvements to the ARM simulator to cope with illegal binaries.Nick Clifton2016-07-143-4/+13
* Add support for simulating big-endian AArch64 binaries.Jim Wilson2016-06-303-9/+30
* Add support for FMLA (by element) to AArch64 sim.Nick Clifton2016-05-062-2/+77
* Fix a typo in the check for SNANs in the RX simulator.Nick Clifton2016-04-272-1/+7
* Add support for the --trace-decode option to the AArch64 simulator.Nick Clifton2016-04-272-7/+317
* Fix primary reason why the SH simulation hasn't been working on 64 bit hosts.Oleg Endo2016-04-103-37/+21
* Move ChangeLog entries from sim/ChangeLog to sim/sh/ChangeLog.Oleg Endo2016-04-102-5/+5
* Adjust default memory size and stack base address for SH simulator.Oleg Endo2016-04-092-3/+8