1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
|
# sh testcase for movua
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
movua_1:
set_grs_a5a5
mov.l srcp, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x03020100
.else
assertreg0 0x00010203
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x04030201
.else
assertreg0 0x01020304
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x05040302
.else
assertreg0 0x02030405
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x06050403
.else
assertreg0 0x03040506
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x07060504
.else
assertreg0 0x04050607
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x08070605
.else
assertreg0 0x05060708
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x09080706
.else
assertreg0 0x06070809
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0a090807
.else
assertreg0 0x0708090a
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0b0a0908
.else
assertreg0 0x08090a0b
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0c0b0a09
.else
assertreg0 0x090a0b0c
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0d0c0b0a
.else
assertreg0 0x0a0b0c0d
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0e0d0c0b
.else
assertreg0 0x0b0c0d0e
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0f0e0d0c
.else
assertreg0 0x0c0d0e0f
.endif
assertreg src+12, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
bra movua_4:
nop
.align 0
src: .byte 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
.align 2
srcp: .long src
movua_4:
set_grs_a5a5
mov.l srcp2, r1
movua.l @r1+, r0
.ifdef LITTLE
assertreg0 0x03020100
.else
assertreg0 0x00010203
.endif
assertreg src+4, r1
mov.l srcp2, r1
add #1, r1
movua.l @r1+, r0
.ifdef LITTLE
assertreg0 0x04030201
.else
assertreg0 0x01020304
.endif
assertreg src+5, r1
mov.l srcp2, r1
add #2, r1
movua.l @r1+, r0
.ifdef LITTLE
assertreg0 0x05040302
.else
assertreg0 0x02030405
.endif
assertreg src+6, r1
mov.l srcp2, r1
add #3, r1
movua.l @r1+, r0
.ifdef LITTLE
assertreg0 0x06050403
.else
assertreg0 0x03040506
.endif
assertreg src+7, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
srcp2: .long src
|
