gas:

2009-01-29  Mark Mitchell  <mark@codesourcery.com>

	* config/tc-arm.c (do_t_orn): New function.
	(do_t_rrx): Likewise.
	(insns): Add orn and rrx.

gas/testsuite:
2009-01-29  Mark Mitchell  <mark@codesourcery.com>

	* gas/arm/thumb32.s: Add tests for orn and rrx.
	* gas/arm/thumb32.d: Adjust accordingly.
	* gas/arm/thumb32.l: Likewise.
	* gas/arm/thumb2_invert.s: Add tests for orn and orr.
	* gas/arm/thumb2_invert.d: Adjust accordingly.
	* gas/arm/tcompat.s: Add tests for rrx.
	* gas/arm/tcompat.d: Adjust accordingly.

10 files changed, 228 insertions, 133 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index ac2afd0b3e..13aac0f86d 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,11 @@
 2009-01-29  Mark Mitchell  <mark@codesourcery.com>
 
+	* config/tc-arm.c (do_t_orn): New function.
+	(do_t_rrx): Likewise.
+	(insns): Add orn and rrx.
+
+2009-01-29  Mark Mitchell  <mark@codesourcery.com>
+
 	* config/tc-arm.c (insns): Add qasx, qsax, shasx, shsax, ssax,
 	uasx, uhasx, uhsx, uqasx, uqsax, usax. 
 
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 8472798b7d..a8fe66715b 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10015,6 +10015,35 @@ do_t_neg (void)
 }
 
 static void
+do_t_orn (void)
+{
+  unsigned Rd, Rn;
+
+  Rd = inst.operands[0].reg;
+  Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
+
+  inst.instruction |= Rd << 8;
+  inst.instruction |= Rn << 16;
+
+  if (!inst.operands[2].isreg)
+    {
+      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
+      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+    }
+  else
+    {
+      unsigned Rm;
+
+      Rm = inst.operands[2].reg;
+
+      constraint (inst.operands[2].shifted
+		  && inst.operands[2].immisreg,
+		  _("shift must be constant"));
+      encode_thumb32_shifted_operand (2);
+    }
+}
+
+static void
 do_t_pkhbt (void)
 {
   inst.instruction |= inst.operands[0].reg << 8;
@@ -10108,6 +10137,18 @@ do_t_rev (void)
 }
 
 static void
+do_t_rrx (void)
+{
+  unsigned Rd, Rm;
+
+  Rd = inst.operands[0].reg;
+  Rm = inst.operands[1].reg;
+
+  inst.instruction |= Rd << 8;
+  inst.instruction |= Rm;
+}
+
+static void
 do_t_rsb (void)
 {
   int Rd, Rs;
@@ -15434,21 +15475,24 @@ static const struct asm_opcode insns[] =
  /* ARM does not really have an IT instruction, so always allow it.  */
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_ext_v1
- TUE(it,        0, bf08, 1, (COND),    it, t_it),
- TUE(itt,       0, bf0c, 1, (COND),    it, t_it),
- TUE(ite,       0, bf04, 1, (COND),    it, t_it),
- TUE(ittt,      0, bf0e, 1, (COND),    it, t_it),
- TUE(itet,      0, bf06, 1, (COND),    it, t_it),
- TUE(itte,      0, bf0a, 1, (COND),    it, t_it),
- TUE(itee,      0, bf02, 1, (COND),    it, t_it),
- TUE(itttt,     0, bf0f, 1, (COND),    it, t_it),
- TUE(itett,     0, bf07, 1, (COND),    it, t_it),
- TUE(ittet,     0, bf0b, 1, (COND),    it, t_it),
- TUE(iteet,     0, bf03, 1, (COND),    it, t_it),
- TUE(ittte,     0, bf0d, 1, (COND),    it, t_it),
- TUE(itete,     0, bf05, 1, (COND),    it, t_it),
- TUE(ittee,     0, bf09, 1, (COND),    it, t_it),
- TUE(iteee,     0, bf01, 1, (COND),    it, t_it),
+ TUE(it,        0,        bf08,     1, (COND),   it,    t_it),
+ TUE(itt,       0,        bf0c,     1, (COND),   it,    t_it),
+ TUE(ite,       0,        bf04,     1, (COND),   it,    t_it),
+ TUE(ittt,      0,        bf0e,     1, (COND),   it,    t_it),
+ TUE(itet,      0,        bf06,     1, (COND),   it,    t_it),
+ TUE(itte,      0,        bf0a,     1, (COND),   it,    t_it),
+ TUE(itee,      0,        bf02,     1, (COND),   it,    t_it),
+ TUE(itttt,     0,        bf0f,     1, (COND),   it,    t_it),
+ TUE(itett,     0,        bf07,     1, (COND),   it,    t_it),
+ TUE(ittet,     0,        bf0b,     1, (COND),   it,    t_it),
+ TUE(iteet,     0,        bf03,     1, (COND),   it,    t_it),
+ TUE(ittte,     0,        bf0d,     1, (COND),   it,    t_it),
+ TUE(itete,     0,        bf05,     1, (COND),   it,    t_it),
+ TUE(ittee,     0,        bf09,     1, (COND),   it,    t_it),
+ TUE(iteee,     0,        bf01,     1, (COND),   it,    t_it),
+ /* ARM/Thumb-2 instructions with no Thumb-1 equivalent.  */
+ TC3(rrx,       01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
+ TC3(rrxs,      01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
 
  /* Thumb2 only instructions.  */
 #undef ARM_VARIANT
@@ -15456,6 +15500,8 @@ static const struct asm_opcode insns[] =
 
  TCE(addw,	0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
  TCE(subw,	0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
+ TCE(orn,       0, ea600000, 3, (RR, oRR, SH),  0, t_orn),
+ TCE(orns,      0, ea700000, 3, (RR, oRR, SH),  0, t_orn),
  TCE(tbb,       0, e8d0f000, 1, (TB), 0, t_tb),
  TCE(tbh,       0, e8d0f010, 1, (TB), 0, t_tb),
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 88953665ae..6b14d43af2 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,15 @@
 2009-01-29  Mark Mitchell  <mark@codesourcery.com>
 
+	* gas/arm/thumb32.s: Add tests for orn and rrx.
+	* gas/arm/thumb32.d: Adjust accordingly.
+	* gas/arm/thumb32.l: Likewise.
+	* gas/arm/thumb2_invert.s: Add tests for orn and orr.
+	* gas/arm/thumb2_invert.d: Adjust accordingly.
+	* gas/arm/tcompat.s: Add tests for rrx.
+	* gas/arm/tcompat.d: Adjust accordingly.
+
+2009-01-29  Mark Mitchell  <mark@codesourcery.com>
+
 	* gas/arm/thumb32.s (qadd): Add tests for them.
 	* gas/arm/thumb32.d: Adjust accordingly.
 
diff --git a/gas/testsuite/gas/arm/tcompat.d b/gas/testsuite/gas/arm/tcompat.d
index be7afae7a4..b333a31436 100644
--- a/gas/testsuite/gas/arm/tcompat.d
+++ b/gas/testsuite/gas/arm/tcompat.d
@@ -48,3 +48,7 @@ Disassembly of section .text:
 0+94 <[^>]*> e1c00001 ?	bic	r0, r0, r1
 0+98 <[^>]*> e0000091 ?	mul	r0, r1, r0
 0+9c <[^>]*> e1a00000 ?	nop			\(mov r0,r0\)
+0+a0 <[^>]*> e1a00069 ?	rrx	r0, r9
+0+a4 <[^>]*> e1b09060 ?	rrxs	r9, r0
+0+a8 <[^>]*> e1a00000 ?	nop			\(mov r0,r0\)
+0+ac <[^>]*> e1a00000 ?	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/tcompat.s b/gas/testsuite/gas/arm/tcompat.s
index c0042e8f12..98b930319e 100644
--- a/gas/testsuite/gas/arm/tcompat.s
+++ b/gas/testsuite/gas/arm/tcompat.s
@@ -43,3 +43,8 @@ l:
 	bic	r0,r1
 	mul	r0,r1
 	nop
+
+	rrx	r0,r9
+	rrxs	r9,r0
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/thumb2_invert.d b/gas/testsuite/gas/arm/thumb2_invert.d
index 3880e5bb5f..75a37bae22 100644
--- a/gas/testsuite/gas/arm/thumb2_invert.d
+++ b/gas/testsuite/gas/arm/thumb2_invert.d
@@ -14,3 +14,5 @@ Disassembly of section .text:
 0+01c <[^>]+> f002 4800 	and.w	r8, r2, #2147483648	; 0x80000000
 0+020 <[^>]+> f06f 4300 	mvn.w	r3, #2147483648	; 0x80000000
 0+024 <[^>]+> f04f 4100 	mov.w	r1, #2147483648	; 0x80000000
+0+028 <[^>]+> f062 4600 	orn	r6, r2, #2147483648	; 0x80000000
+0+02c <[^>]+> f042 4800 	orr.w	r8, r2, #2147483648	; 0x80000000
diff --git a/gas/testsuite/gas/arm/thumb2_invert.s b/gas/testsuite/gas/arm/thumb2_invert.s
index 38ebcdda4c..e72e63c1d3 100644
--- a/gas/testsuite/gas/arm/thumb2_invert.s
+++ b/gas/testsuite/gas/arm/thumb2_invert.s
@@ -12,3 +12,5 @@ thumb2_invert:
 	bic	r8, r2, #0x7fffffff
 	mov	r3, 0x7fffffff
 	mvn	r1, 0x7fffffff
+	orr	r6, r2, #0x7fffffff
+	orn	r8, r2, #0x7fffffff
diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
index e77ed2f6d1..1e872413ad 100644
--- a/gas/testsuite/gas/arm/thumb32.d
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -205,6 +205,19 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> eb70 0000 	sbcs\.w	r0, r0, r0
 0[0-9a-f]+ <[^>]+> eb61 4062 	sbc\.w	r0, r1, r2, asr #17
 0[0-9a-f]+ <[^>]+> f161 0081 	sbc\.w	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> ea70 0000 	orns	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ea75 0500 	orns	r5, r5, r0
+0[0-9a-f]+ <[^>]+> ea70 0005 	orns	r0, r0, r5
+0[0-9a-f]+ <[^>]+> ea70 0005 	orns	r0, r0, r5
+0[0-9a-f]+ <[^>]+> ea75 0000 	orns	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ea65 0000 	orn	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ea61 0002 	orn	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ea60 0900 	orn	r9, r0, r0
+0[0-9a-f]+ <[^>]+> ea69 0000 	orn	r0, r9, r0
+0[0-9a-f]+ <[^>]+> ea60 0009 	orn	r0, r0, r9
+0[0-9a-f]+ <[^>]+> ea70 0000 	orns	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ea61 4062 	orn	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f061 0081 	orn	r0, r1, #129	; 0x81
 0[0-9a-f]+ <[^>]+> f36f 0000 	bfc	r0, #0, #1
 0[0-9a-f]+ <[^>]+> f36f 0900 	bfc	r9, #0, #1
 0[0-9a-f]+ <[^>]+> f36f 0900 	bfc	r9, #0, #1
@@ -220,97 +233,97 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f349 0000 	sbfx	r0, r9, #0, #1
 0[0-9a-f]+ <[^>]+> f3c0 5040 	ubfx	r0, r0, #21, #1
 0[0-9a-f]+ <[^>]+> f340 0011 	sbfx	r0, r0, #0, #18
-0[0-9a-f]+ <[^>]+> d0fe      	beq\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d02a      	beq\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d1fc      	bne\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d128      	bne\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d2fa      	bcs\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d226      	bcs\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d2f8      	bcs\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d224      	bcs\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d3f6      	bcc\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d322      	bcc\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d3f4      	bcc\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d320      	bcc\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d3f2      	bcc\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d31e      	bcc\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d4f0      	bmi\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d41c      	bmi\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d5ee      	bpl\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d51a      	bpl\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d6ec      	bvs\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d618      	bvs\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d7ea      	bvc\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d716      	bvc\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d8e8      	bhi\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d814      	bhi\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d9e6      	bls\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d912      	bls\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d7e4      	bvc\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d710      	bvc\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d8e2      	bhi\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d80e      	bhi\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> d9e0      	bls\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> d90c      	bls\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> dade      	bge\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> da0a      	bge\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> dbdc      	blt\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> db08      	blt\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> dcda      	bgt\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> dc06      	bgt\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> ddd8      	ble\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> dd04      	ble\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> e7d6      	b\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> e002      	b\.n	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> e7d4      	b\.n	0+2ca <[^>]+>
-0[0-9a-f]+ <[^>]+> e000      	b\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d0fe      	beq\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d02a      	beq\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d1fc      	bne\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d128      	bne\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d2fa      	bcs\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d226      	bcs\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d2f8      	bcs\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d224      	bcs\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d3f6      	bcc\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d322      	bcc\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d3f4      	bcc\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d320      	bcc\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d3f2      	bcc\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d31e      	bcc\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d4f0      	bmi\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d41c      	bmi\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d5ee      	bpl\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d51a      	bpl\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d6ec      	bvs\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d618      	bvs\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d7ea      	bvc\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d716      	bvc\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d8e8      	bhi\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d814      	bhi\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d9e6      	bls\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d912      	bls\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d7e4      	bvc\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d710      	bvc\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d8e2      	bhi\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d80e      	bhi\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> d9e0      	bls\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> d90c      	bls\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> dade      	bge\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> da0a      	bge\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> dbdc      	blt\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> db08      	blt\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> dcda      	bgt\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> dc06      	bgt\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> ddd8      	ble\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> dd04      	ble\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> e7d6      	b\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> e002      	b\.n	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> e7d4      	b\.n	0+2fe <[^>]+>
+0[0-9a-f]+ <[^>]+> e000      	b\.n	0+358 <[^>]+>
 0[0-9a-f]+ <[^>]+> 46c0      	nop			\(mov r8, r8\)
-0[0-9a-f]+ <[^>]+> f43f affe 	beq\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f000 8058 	beq\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f47f affa 	bne\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f040 8054 	bne\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f4bf aff6 	bcs\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f080 8050 	bcs\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f4bf aff2 	bcs\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f080 804c 	bcs\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f4ff afee 	bcc\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f0c0 8048 	bcc\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f4ff afea 	bcc\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f0c0 8044 	bcc\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f4ff afe6 	bcc\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f0c0 8040 	bcc\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f53f afe2 	bmi\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f100 803c 	bmi\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f57f afde 	bpl\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f140 8038 	bpl\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f5bf afda 	bvs\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f180 8034 	bvs\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f5ff afd6 	bvc\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f1c0 8030 	bvc\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f63f afd2 	bhi\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f200 802c 	bhi\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f67f afce 	bls\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f240 8028 	bls\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f5ff afca 	bvc\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f1c0 8024 	bvc\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f63f afc6 	bhi\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f200 8020 	bhi\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f67f afc2 	bls\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f240 801c 	bls\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f6bf afbe 	bge\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f280 8018 	bge\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f6ff afba 	blt\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f2c0 8014 	blt\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f73f afb6 	bgt\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f300 8010 	bgt\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f77f afb2 	ble\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f340 800c 	ble\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f7ff bfae 	b\.w	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f000 b808 	b\.w	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f7ff ffaa 	bl	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f000 f804 	bl	0+3dc <[^>]+>
-0[0-9a-f]+ <[^>]+> f7ff efa6 	blx	0+324 <[^>]+>
-0[0-9a-f]+ <[^>]+> f000 e800 	blx	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f43f affe 	beq\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f000 8058 	beq\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f47f affa 	bne\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f040 8054 	bne\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f4bf aff6 	bcs\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f080 8050 	bcs\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f4bf aff2 	bcs\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f080 804c 	bcs\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f4ff afee 	bcc\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f0c0 8048 	bcc\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f4ff afea 	bcc\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f0c0 8044 	bcc\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f4ff afe6 	bcc\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f0c0 8040 	bcc\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f53f afe2 	bmi\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f100 803c 	bmi\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f57f afde 	bpl\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f140 8038 	bpl\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f5bf afda 	bvs\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f180 8034 	bvs\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f5ff afd6 	bvc\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f1c0 8030 	bvc\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f63f afd2 	bhi\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f200 802c 	bhi\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f67f afce 	bls\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f240 8028 	bls\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f5ff afca 	bvc\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f1c0 8024 	bvc\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f63f afc6 	bhi\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f200 8020 	bhi\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f67f afc2 	bls\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f240 801c 	bls\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f6bf afbe 	bge\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f280 8018 	bge\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f6ff afba 	blt\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f2c0 8014 	blt\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f73f afb6 	bgt\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f300 8010 	bgt\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f77f afb2 	ble\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f340 800c 	ble\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f7ff bfae 	b\.w	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f000 b808 	b\.w	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f7ff ffaa 	bl	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f000 f804 	bl	0+410 <[^>]+>
+0[0-9a-f]+ <[^>]+> f7ff efa6 	blx	0+358 <[^>]+>
+0[0-9a-f]+ <[^>]+> f000 e800 	blx	0+410 <[^>]+>
 0[0-9a-f]+ <[^>]+> 4748      	bx	r9
 0[0-9a-f]+ <[^>]+> 4780      	blx	r0
 0[0-9a-f]+ <[^>]+> 47c8      	blx	r9
@@ -335,8 +348,8 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> ea4f 0000 	mov\.w	r0, r0
 0[0-9a-f]+ <[^>]+> ea4f 0900 	mov\.w	r9, r0
 0[0-9a-f]+ <[^>]+> ea4f 0009 	mov\.w	r0, r9
-0[0-9a-f]+ <[^>]+> b910      	cbnz	r0, 0+432 <[^>]+>
-0[0-9a-f]+ <[^>]+> b105      	cbz	r5, 0+430 <[^>]+>
+0[0-9a-f]+ <[^>]+> b910      	cbnz	r0, 0+466 <[^>]+>
+0[0-9a-f]+ <[^>]+> b105      	cbz	r5, 0+464 <[^>]+>
 0[0-9a-f]+ <[^>]+> bf00      	nop
 0[0-9a-f]+ <[^>]+> bf10      	yield
 0[0-9a-f]+ <[^>]+> bf20      	wfe
@@ -516,8 +529,8 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f815 fd30 	pld	\[r5, #-48\]!
 0[0-9a-f]+ <[^>]+> f815 f004 	pld	\[r5, r4\]
 0[0-9a-f]+ <[^>]+> f819 f00c 	pld	\[r9, ip\]
-0[0-9a-f]+ <[^>]+> f89f f006 	pld	\[pc, #6\]	; 0+5ba <[^>]+>
-0[0-9a-f]+ <[^>]+> f81f f02a 	pld	\[pc, #-42\]	; 0+58e <[^>]+>
+0[0-9a-f]+ <[^>]+> f89f f006 	pld	\[pc, #6\]	; 0+5ee <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f f02a 	pld	\[pc, #-42\]	; 0+5c2 <[^>]+>
 0[0-9a-f]+ <[^>]+> e9d5 2300 	ldrd	r2, r3, \[r5\]
 0[0-9a-f]+ <[^>]+> e9d5 230c 	ldrd	r2, r3, \[r5, #48\]
 0[0-9a-f]+ <[^>]+> e955 230c 	ldrd	r2, r3, \[r5, #-48\]
@@ -827,6 +840,8 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> fa60 f009 	ror\.w	r0, r0, r9
 0[0-9a-f]+ <[^>]+> fa60 f005 	ror\.w	r0, r0, r5
 0[0-9a-f]+ <[^>]+> fa71 f002 	rors\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ea4f 0132 	mov.w	r1, r2, rrx
+0[0-9a-f]+ <[^>]+> ea5f 0334 	movs.w	r3, r4, rrx
 0[0-9a-f]+ <[^>]+> f7f0 8000 	smc	#0	; 0x0
 0[0-9a-f]+ <[^>]+> f7fd 8bca 	smc	#43981	; 0xabcd
 0[0-9a-f]+ <[^>]+> fb10 0000 	smlabb	r0, r0, r0, r0
@@ -929,26 +944,26 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> fa52 f183 	uxtab	r1, r2, r3
 0[0-9a-f]+ <[^>]+> fa32 f183 	uxtab16	r1, r2, r3
 0[0-9a-f]+ <[^>]+> fa12 f183 	uxtah	r1, r2, r3
-0[0-9a-f]+ <[^>]+> f89f 12aa 	ldrb\.w	r1, \[pc, #682\]	; 0+e42 <[^>]+>
-0[0-9a-f]+ <[^>]+> f89f 1155 	ldrb\.w	r1, \[pc, #341\]	; 0+cf1 <[^>]+>
-0[0-9a-f]+ <[^>]+> f81f 12aa 	ldrb\.w	r1, \[pc, #-682\]	; 0+8f6 <[^>]+>
-0[0-9a-f]+ <[^>]+> f81f 1155 	ldrb\.w	r1, \[pc, #-341\]	; 0+a4f <[^>]+>
-0[0-9a-f]+ <[^>]+> f99f 12aa 	ldrsb\.w	r1, \[pc, #682\]	; 0+e52 <[^>]+>
-0[0-9a-f]+ <[^>]+> f99f 1155 	ldrsb\.w	r1, \[pc, #341\]	; 0+d01 <[^>]+>
-0[0-9a-f]+ <[^>]+> f91f 12aa 	ldrsb\.w	r1, \[pc, #-682\]	; 0+906 <[^>]+>
-0[0-9a-f]+ <[^>]+> f91f 1155 	ldrsb\.w	r1, \[pc, #-341\]	; 0+a5f <[^>]+>
-0[0-9a-f]+ <[^>]+> f8bf 12aa 	ldrh\.w	r1, \[pc, #682\]	; 0+e62 <[^>]+>
-0[0-9a-f]+ <[^>]+> f8bf 1155 	ldrh\.w	r1, \[pc, #341\]	; 0+d11 <[^>]+>
-0[0-9a-f]+ <[^>]+> f83f 12aa 	ldrh\.w	r1, \[pc, #-682\]	; 0+916 <[^>]+>
-0[0-9a-f]+ <[^>]+> f83f 1155 	ldrh\.w	r1, \[pc, #-341\]	; 0+a6f <[^>]+>
-0[0-9a-f]+ <[^>]+> f9bf 12aa 	ldrsh\.w	r1, \[pc, #682\]	; 0+e72 <[^>]+>
-0[0-9a-f]+ <[^>]+> f9bf 1155 	ldrsh\.w	r1, \[pc, #341\]	; 0+d21 <[^>]+>
-0[0-9a-f]+ <[^>]+> f93f 12aa 	ldrsh\.w	r1, \[pc, #-682\]	; 0+926 <[^>]+>
-0[0-9a-f]+ <[^>]+> f93f 1155 	ldrsh\.w	r1, \[pc, #-341\]	; 0+a7f <[^>]+>
-0[0-9a-f]+ <[^>]+> f8df 12aa 	ldr\.w	r1, \[pc, #682\]	; 0+e82 <[^>]+>
-0[0-9a-f]+ <[^>]+> f8df 1155 	ldr\.w	r1, \[pc, #341\]	; 0+d31 <[^>]+>
-0[0-9a-f]+ <[^>]+> f85f 12aa 	ldr\.w	r1, \[pc, #-682\]	; 0+936 <[^>]+>
-0[0-9a-f]+ <[^>]+> f85f 1155 	ldr\.w	r1, \[pc, #-341\]	; 0+a8f <[^>]+>
+0[0-9a-f]+ <[^>]+> f89f 12aa 	ldrb\.w	r1, \[pc, #682\]	; 0+e7e <[^>]+>
+0[0-9a-f]+ <[^>]+> f89f 1155 	ldrb\.w	r1, \[pc, #341\]	; 0+d2d <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f 12aa 	ldrb\.w	r1, \[pc, #-682\]	; 0+932 <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f 1155 	ldrb\.w	r1, \[pc, #-341\]	; 0+a8b <[^>]+>
+0[0-9a-f]+ <[^>]+> f99f 12aa 	ldrsb\.w	r1, \[pc, #682\]	; 0+e8e <[^>]+>
+0[0-9a-f]+ <[^>]+> f99f 1155 	ldrsb\.w	r1, \[pc, #341\]	; 0+d3d <[^>]+>
+0[0-9a-f]+ <[^>]+> f91f 12aa 	ldrsb\.w	r1, \[pc, #-682\]	; 0+942 <[^>]+>
+0[0-9a-f]+ <[^>]+> f91f 1155 	ldrsb\.w	r1, \[pc, #-341\]	; 0+a9b <[^>]+>
+0[0-9a-f]+ <[^>]+> f8bf 12aa 	ldrh\.w	r1, \[pc, #682\]	; 0+e9e <[^>]+>
+0[0-9a-f]+ <[^>]+> f8bf 1155 	ldrh\.w	r1, \[pc, #341\]	; 0+d4d <[^>]+>
+0[0-9a-f]+ <[^>]+> f83f 12aa 	ldrh\.w	r1, \[pc, #-682\]	; 0+952 <[^>]+>
+0[0-9a-f]+ <[^>]+> f83f 1155 	ldrh\.w	r1, \[pc, #-341\]	; 0+aab <[^>]+>
+0[0-9a-f]+ <[^>]+> f9bf 12aa 	ldrsh\.w	r1, \[pc, #682\]	; 0+eae <[^>]+>
+0[0-9a-f]+ <[^>]+> f9bf 1155 	ldrsh\.w	r1, \[pc, #341\]	; 0+d5d <[^>]+>
+0[0-9a-f]+ <[^>]+> f93f 12aa 	ldrsh\.w	r1, \[pc, #-682\]	; 0+962 <[^>]+>
+0[0-9a-f]+ <[^>]+> f93f 1155 	ldrsh\.w	r1, \[pc, #-341\]	; 0+abb <[^>]+>
+0[0-9a-f]+ <[^>]+> f8df 12aa 	ldr\.w	r1, \[pc, #682\]	; 0+ebe <[^>]+>
+0[0-9a-f]+ <[^>]+> f8df 1155 	ldr\.w	r1, \[pc, #341\]	; 0+d6d <[^>]+>
+0[0-9a-f]+ <[^>]+> f85f 12aa 	ldr\.w	r1, \[pc, #-682\]	; 0+972 <[^>]+>
+0[0-9a-f]+ <[^>]+> f85f 1155 	ldr\.w	r1, \[pc, #-341\]	; 0+acb <[^>]+>
 0[0-9a-f]+ <[^>]+> f200 0900 	addw	r9, r0, #0	; 0x0
 0[0-9a-f]+ <[^>]+> f60f 76ff 	addw	r6, pc, #4095	; 0xfff
 0[0-9a-f]+ <[^>]+> f6a9 2685 	subw	r6, r9, #2693	; 0xa85
diff --git a/gas/testsuite/gas/arm/thumb32.l b/gas/testsuite/gas/arm/thumb32.l
index c687beac79..eb404f29b2 100644
--- a/gas/testsuite/gas/arm/thumb32.l
+++ b/gas/testsuite/gas/arm/thumb32.l
@@ -1,8 +1,4 @@
 [^;]*: Assembler messages:
-[^;]*:446: Warning: s suffix on comparison instruction is deprecated
-[^;]*:446: Warning: s suffix on comparison instruction is deprecated
-[^;]*:446: Warning: s suffix on comparison instruction is deprecated
-[^;]*:446: Warning: s suffix on comparison instruction is deprecated
 [^;]*:447: Warning: s suffix on comparison instruction is deprecated
 [^;]*:447: Warning: s suffix on comparison instruction is deprecated
 [^;]*:447: Warning: s suffix on comparison instruction is deprecated
@@ -15,3 +11,7 @@
 [^;]*:449: Warning: s suffix on comparison instruction is deprecated
 [^;]*:449: Warning: s suffix on comparison instruction is deprecated
 [^;]*:449: Warning: s suffix on comparison instruction is deprecated
+[^;]*:450: Warning: s suffix on comparison instruction is deprecated
+[^;]*:450: Warning: s suffix on comparison instruction is deprecated
+[^;]*:450: Warning: s suffix on comparison instruction is deprecated
+[^;]*:450: Warning: s suffix on comparison instruction is deprecated
diff --git a/gas/testsuite/gas/arm/thumb32.s b/gas/testsuite/gas/arm/thumb32.s
index 2757899216..de4eb1ed12 100644
--- a/gas/testsuite/gas/arm/thumb32.s
+++ b/gas/testsuite/gas/arm/thumb32.s
@@ -153,6 +153,7 @@ arit3:
 	arit3	orr orrs orr.w orrs.w
 	arit3	rsb rsbs rsb.w rsbs.w
 	arit3	sbc sbcs sbc.w sbcs.w
+	arit3	orn orns orn orns
 
 	.purgem arit3
 
@@ -625,6 +626,10 @@ shift:
 
 	.purgem sh
 
+rrx:	
+	rrx	r1, r2
+	rrxs	r3, r4
+
 smc:
 	smc	#0
 	smc	#0xabcd