diff options
| author | Kazu Hirata <kazu@codesourcery.com> | 2000-11-16 20:48:09 +0000 |
|---|---|---|
| committer | Kazu Hirata <kazu@codesourcery.com> | 2000-11-16 20:48:09 +0000 |
| commit | 11b0bd5bb08973f680edb4bb330b48f206cfea60 (patch) | |
| tree | fa00eaa8dd99473d87bf48ffd48d38e11ee72845 /bfd/cpu-ia64-opc.c | |
| parent | 2a57c843beaa4b762206daa14ca04e9502c009fc (diff) | |
| download | binutils-redhat-11b0bd5bb08973f680edb4bb330b48f206cfea60.tar.gz | |
2000-11-16 Kazu Hirata <kazu@hxi.com>
* cpu-a29k.c: Fix formatting.
* cpu-alpha.c: Likewise.
* cpu-arm.c: Likewise.
* cpu-avr.c: Likewise.
* cpu-d10v.c: Likewise.
* cpu-h8500.c: Likewise.
* cpu-hppa.c: Likewise.
* cpu-i370.c: Likewise.
* cpu-i386.c: Likewise.
* cpu-i960.c: Likewise.
* cpu-ia64-opc.c: Likewise.
* cpu-ia64.c: Likewise.
* cpu-m32r.c: Likewise.
* cpu-m68hc11.c: Likewise.
* cpu-m68hc12.c: Likewise.
* cpu-m68k.c: Likewise.
* cpu-m88k.c: Likewise.
* cpu-mips.c: Likewise.
* cpu-ns32k.c: Likewise.
* cpu-pj.c: Likewise.
* cpu-powerpc.c: Likewise.
* cpu-sh.c: Likewise.
* cpu-sparc.c: Likewise.
* cpu-tic54x.c: Likewise.
* cpu-v850.c: Likewise.
* cpu-vax.c: Likewise.
* cpu-w65.c: Likewise.
* cpu-we32k.c: Likewise.
* cpu-z8k.c: Likewise.
Diffstat (limited to 'bfd/cpu-ia64-opc.c')
| -rw-r--r-- | bfd/cpu-ia64-opc.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/bfd/cpu-ia64-opc.c b/bfd/cpu-ia64-opc.c index 130dbe7b99..36de3c818e 100644 --- a/bfd/cpu-ia64-opc.c +++ b/bfd/cpu-ia64-opc.c @@ -17,7 +17,6 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - /* Logically, this code should be part of libopcode but since some of the operand insertion/extraction functions help bfd to implement relocations, this code is included as part of elf64-ia64.c. This @@ -555,7 +554,7 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] = { ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */ "a 44-bit unsigned (least 16 bits ignored/zeroes)" }, { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */ - "a 62-bit unsigned" }, + "a 62-bit unsigned" }, { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */ "a 64-bit unsigned" }, { ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */ @@ -580,7 +579,7 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] = {{ 7, 6}, {13, 20}, { 1, 36}}, 0, "a branch target" }, { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */ - "a branch target" }, - { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */ + "a branch target" }, + { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */ "a branch target" }, }; |