Add support for 64-bit ARM architecture: AArch64

5 files changed, 315 insertions, 7 deletions

diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am
index 1fd3e1b4fe..fc69005530 100644
--- a/gas/doc/Makefile.am
+++ b/gas/doc/Makefile.am
@@ -29,6 +29,7 @@ asconfig.texi: $(CONFIG).texi
 	chmod u+w ./asconfig.texi
 
 CPU_DOCS = \
+	c-aarch64.texi \
 	c-alpha.texi \
 	c-arc.texi \
 	c-arm.texi \
diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in
index 4893f03f1d..5149e02274 100644
--- a/gas/doc/Makefile.in
+++ b/gas/doc/Makefile.in
@@ -38,7 +38,9 @@ subdir = doc
 DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \
 	$(as_TEXINFOS)
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
+am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
+	$(top_srcdir)/../config/zlib.m4 \
+	$(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../config/acx.m4 \
 	$(top_srcdir)/../config/depstand.m4 \
 	$(top_srcdir)/../config/gettext-sister.m4 \
 	$(top_srcdir)/../config/largefile.m4 \
@@ -49,9 +51,9 @@ am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
 	$(top_srcdir)/../config/plugins.m4 \
 	$(top_srcdir)/../config/po.m4 \
 	$(top_srcdir)/../config/progtest.m4 \
-	$(top_srcdir)/../bfd/acinclude.m4 \
-	$(top_srcdir)/../config/zlib.m4 \
-	$(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/acinclude.m4 \
+	$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
+	$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
+	$(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/acinclude.m4 \
 	$(top_srcdir)/configure.in
 am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
 	$(ACLOCAL_M4)
@@ -118,7 +120,6 @@ CYGPATH_W = @CYGPATH_W@
 DATADIRNAME = @DATADIRNAME@
 DEFS = @DEFS@
 DEPDIR = @DEPDIR@
-DLLTOOL = @DLLTOOL@
 DSYMUTIL = @DSYMUTIL@
 DUMPBIN = @DUMPBIN@
 ECHO_C = @ECHO_C@
@@ -154,7 +155,6 @@ LN_S = @LN_S@
 LTLIBOBJS = @LTLIBOBJS@
 MAINT = @MAINT@
 MAKEINFO = @MAKEINFO@
-MANIFEST_TOOL = @MANIFEST_TOOL@
 MKDIR_P = @MKDIR_P@
 MKINSTALLDIRS = @MKINSTALLDIRS@
 MSGFMT = @MSGFMT@
@@ -191,7 +191,6 @@ abs_builddir = @abs_builddir@
 abs_srcdir = @abs_srcdir@
 abs_top_builddir = @abs_top_builddir@
 abs_top_srcdir = @abs_top_srcdir@
-ac_ct_AR = @ac_ct_AR@
 ac_ct_CC = @ac_ct_CC@
 ac_ct_DUMPBIN = @ac_ct_DUMPBIN@
 am__include = @am__include@
@@ -271,6 +270,7 @@ TEXI2DVI = texi2dvi -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
 		   -I "$(top_srcdir)/../bfd/doc" -I ../../bfd/doc
 
 CPU_DOCS = \
+	c-aarch64.texi \
 	c-alpha.texi \
 	c-arc.texi \
 	c-arm.texi \
diff --git a/gas/doc/all.texi b/gas/doc/all.texi
index 9a55441cb3..e294208e86 100644
--- a/gas/doc/all.texi
+++ b/gas/doc/all.texi
@@ -26,6 +26,7 @@
 
 @c CPUs of interest
 @c ================
+@set AARCH64
 @set ALPHA
 @set ARC
 @set ARM
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 5b5d268b10..942d25d59e 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -249,6 +249,11 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 @c
 @c Target dependent options are listed below.  Keep the list sorted.
 @c Add an empty line for separation.
+@ifset AARCH64
+
+@emph{Target AArch64 options:}
+   [@b{-EB}|@b{-EL}]
+@end ifset
 @ifset ALPHA
 
 @emph{Target Alpha options:}
@@ -733,6 +738,25 @@ Standard input, or source files to assemble.
 @end table
 @c man end
 
+@ifset AARCH64
+
+@ifclear man
+@xref{AArch64 Options}, for the options available when @value{AS} is configured
+for the 64-bit mode of the ARM Architecture (AArch64).
+@end ifclear
+
+@ifset man
+@c man begin OPTIONS
+The following options are available when @value{AS} is configured for the
+64-bit mode of the ARM Architecture (AArch64).
+@c man end
+@c man begin INCLUDE
+@include c-aarch64.texi
+@c ended inside the included file
+@end ifset
+
+@end ifset
+
 @ifset ALPHA
 
 @ifclear man
@@ -6914,6 +6938,9 @@ include details on any machine's instruction set.  For details on that
 subject, see the hardware manufacturer's manual.
 
 @menu
+@ifset AARCH64
+* AArch64-Dependent::		AArch64 Dependent Features
+@end ifset
 @ifset ALPHA
 * Alpha-Dependent::		Alpha Dependent Features
 @end ifset
@@ -7072,6 +7099,10 @@ subject, see the hardware manufacturer's manual.
 @c node and sectioning commands; hence the repetition of @chapter BLAH
 @c in both conditional blocks.
 
+@ifset AARCH64
+@include c-aarch64.texi
+@end ifset
+
 @ifset ALPHA
 @include c-alpha.texi
 @end ifset
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
new file mode 100644
index 0000000000..5a59f449ac
--- /dev/null
+++ b/gas/doc/c-aarch64.texi
@@ -0,0 +1,275 @@
+@c Copyright 2009, 2010, 2011, 2012  Free Software Foundation, Inc.
+@c Contributed by ARM Ltd.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@c man end
+
+@ifset GENERIC
+@page
+@node AArch64-Dependent
+@chapter AArch64 Dependent Features
+@end ifset
+
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter AArch64 Dependent Features
+@end ifclear
+
+@cindex AArch64 support
+@cindex Thumb support
+@menu
+* AArch64 Options::              Options
+* AArch64 Syntax::               Syntax
+* AArch64 Floating Point::       Floating Point
+* AArch64 Directives::           AArch64 Machine Directives
+* AArch64 Opcodes::              Opcodes
+* AArch64 Mapping Symbols::      Mapping Symbols
+@end menu
+
+@node AArch64 Options
+@section Options
+@cindex AArch64 options (none)
+@cindex options for AArch64 (none)
+
+@c man begin OPTIONS
+@table @gcctabopt
+
+@cindex @code{-EB} command line option, AArch64
+@item -EB
+This option specifies that the output generated by the assembler should
+be marked as being encoded for a big-endian processor.
+
+@cindex @code{-EL} command line option, AArch64
+@item -EL
+This option specifies that the output generated by the assembler should
+be marked as being encoded for a little-endian processor.
+
+@end table
+@c man end
+
+@node AArch64 Syntax
+@section Syntax
+@menu
+* AArch64-Chars::                Special Characters
+* AArch64-Regs::                 Register Names
+* AArch64-Relocations::	     Relocations
+@end menu
+
+@node AArch64-Chars
+@subsection Special Characters
+
+@cindex line comment character, AArch64
+@cindex AArch64 line comment character
+The presence of a @samp{//} on a line indicates the start of a comment
+that extends to the end of the current line.  If a @samp{#} appears as
+the first character of a line, the whole line is treated as a comment.
+
+@cindex line separator, AArch64
+@cindex statement separator, AArch64
+@cindex AArch64 line separator
+The @samp{;} character can be used instead of a newline to separate
+statements.
+
+@cindex immediate character, AArch64
+@cindex AArch64 immediate character
+The @samp{#} can be optionally used to indicate immediate operands.
+
+@node AArch64-Regs
+@subsection Register Names
+
+@cindex AArch64 register names
+@cindex register names, AArch64
+Please refer to the section @samp{4.4 Register Names} of
+@samp{ARMv8 Instruction Set Overview}, which is available at
+@uref{http://infocenter.arm.com}.
+
+@node AArch64-Relocations
+@subsection Relocations
+
+@cindex relocations, AArch64
+@cindex AArch64 relocations
+@cindex MOVN, MOVZ and MOVK group relocations, AArch64
+Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
+by prefixing the label with @samp{#:abs_g2:} etc.
+For example to load the 48-bit absolute address of @var{foo} into x0:
+
+@smallexample
+        movz x0, #:abs_g2:foo		// bits 32-47, overflow check
+        movk x0, #:abs_g1_nc:foo	// bits 16-31, no overflow check
+        movk x0, #:abs_g0_nc:foo	// bits  0-15, no overflow check
+@end smallexample
+
+@cindex ADRP, ADD, LDR/STR group relocations, AArch64
+Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
+instructions can be generated by prefixing the label with
+@samp{#:pg_hi21:} and @samp{#:lo12:} respectively.
+
+For example to use 33-bit (+/-4GB) pc-relative addressing to 
+load the address of @var{foo} into x0:
+
+@smallexample
+        adrp x0, #:pg_hi21:foo
+        add  x0, x0, #:lo12:foo
+@end smallexample
+
+Or to load the value of @var{foo} into x0:
+
+@smallexample
+        adrp x0, #:pg_hi21:foo
+        ldr  x0, [x0, #:lo12:foo]
+@end smallexample
+
+Note that @samp{#:pg_hi21:} is optional.
+
+@smallexample
+        adrp x0, foo
+@end smallexample
+
+is equivalent to
+
+@smallexample
+        adrp x0, #:pg_hi21:foo
+@end smallexample
+
+@node AArch64 Floating Point
+@section Floating Point
+
+@cindex floating point, AArch64 (@sc{ieee})
+@cindex AArch64 floating point (@sc{ieee})
+The AArch64 architecture uses @sc{ieee} floating-point numbers.
+
+@node AArch64 Directives
+@section AArch64 Machine Directives
+
+@cindex machine directives, AArch64
+@cindex AArch64 machine directives
+@table @code
+
+@c AAAAAAAAAAAAAAAAAAAAAAAAA
+@c BBBBBBBBBBBBBBBBBBBBBBBBBB
+
+@cindex @code{.bss} directive, AArch64
+@item .bss
+This directive switches to the @code{.bss} section.
+
+@c CCCCCCCCCCCCCCCCCCCCCCCCCC
+@c DDDDDDDDDDDDDDDDDDDDDDDDDD
+@c EEEEEEEEEEEEEEEEEEEEEEEEEE
+@c FFFFFFFFFFFFFFFFFFFFFFFFFF
+@c GGGGGGGGGGGGGGGGGGGGGGGGGG
+@c HHHHHHHHHHHHHHHHHHHHHHHHHH
+@c IIIIIIIIIIIIIIIIIIIIIIIIII
+@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
+@c KKKKKKKKKKKKKKKKKKKKKKKKKK
+@c LLLLLLLLLLLLLLLLLLLLLLLLLL
+
+@cindex @code{.ltorg} directive, AArch64
+@item .ltorg
+This directive causes the current contents of the literal pool to be
+dumped into the current section (which is assumed to be the .text
+section) at the current location (aligned to a word boundary).
+@code{GAS} maintains a separate literal pool for each section and each
+sub-section.  The @code{.ltorg} directive will only affect the literal
+pool of the current section and sub-section.  At the end of assembly
+all remaining, un-empty literal pools will automatically be dumped.
+
+Note - older versions of @code{GAS} would dump the current literal
+pool any time a section change occurred.  This is no longer done, since
+it prevents accurate control of the placement of literal pools.
+
+@c MMMMMMMMMMMMMMMMMMMMMMMMMM
+
+@c NNNNNNNNNNNNNNNNNNNNNNNNNN
+@c OOOOOOOOOOOOOOOOOOOOOOOOOO
+
+@c PPPPPPPPPPPPPPPPPPPPPPPPPP
+
+@cindex @code{.pool} directive, AArch64
+@item .pool
+This is a synonym for .ltorg.
+
+@c QQQQQQQQQQQQQQQQQQQQQQQQQQ
+@c RRRRRRRRRRRRRRRRRRRRRRRRRR
+
+@cindex @code{.req} directive, AArch64
+@item @var{name} .req @var{register name}
+This creates an alias for @var{register name} called @var{name}.  For
+example:
+
+@smallexample
+        foo .req w0
+@end smallexample
+
+@c SSSSSSSSSSSSSSSSSSSSSSSSSS
+
+@c TTTTTTTTTTTTTTTTTTTTTTTTTT
+
+@c UUUUUUUUUUUUUUUUUUUUUUUUUU
+
+@cindex @code{.unreq} directive, AArch64
+@item .unreq @var{alias-name}
+This undefines a register alias which was previously defined using the
+@code{req} directive.  For example:
+
+@smallexample
+        foo .req w0
+        .unreq foo
+@end smallexample
+
+An error occurs if the name is undefined.  Note - this pseudo op can
+be used to delete builtin in register name aliases (eg 'w0').  This
+should only be done if it is really necessary.
+
+@c VVVVVVVVVVVVVVVVVVVVVVVVVV
+
+@c WWWWWWWWWWWWWWWWWWWWWWWWWW
+@c XXXXXXXXXXXXXXXXXXXXXXXXXX
+@c YYYYYYYYYYYYYYYYYYYYYYYYYY
+@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
+
+@end table
+
+@node AArch64 Opcodes
+@section Opcodes
+
+@cindex AArch64 opcodes
+@cindex opcodes for AArch64
+@code{@value{AS}} implements all the standard AArch64 opcodes.  It also
+implements several pseudo opcodes, including several synthetic load
+instructions. 
+
+@table @code
+
+@cindex @code{LDR reg,=<expr>} pseudo op, AArch64
+@item LDR =
+@smallexample
+  ldr <register> , =<expression>
+@end smallexample
+
+The constant expression will be placed into the nearest literal pool (if it not
+already there) and a PC-relative LDR instruction will be generated.
+
+@end table
+
+For more information on the AArch64 instruction set and assembly language
+notation, see @samp{ARMv8 Instruction Set Overview} available at
+@uref{http://infocenter.arm.com}.
+
+
+@node AArch64 Mapping Symbols
+@section Mapping Symbols
+
+The AArch64 ELF specification requires that special symbols be inserted
+into object files to mark certain features:
+
+@table @code
+
+@cindex @code{$x}
+@item $x
+At the start of a region of code containing AArch64 instructions.
+
+@cindex @code{$d}
+@item $d
+At the start of a region of data.
+
+@end table