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author | Julian Brown <julian@codesourcery.com> | 2006-04-26 15:42:17 +0000 |
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committer | Julian Brown <julian@codesourcery.com> | 2006-04-26 15:42:17 +0000 |
commit | 52d1d5dbfb8cca9a1c23bb7e2177c15587d67aed (patch) | |
tree | 01bf90fa00e913575be24bfd96af49aeff432eac /gas/testsuite/gas/arm/neon-ldst-rm.s | |
parent | 6e2a670f70bdd66e56b6fc6b29a6ea8ea4ae65a4 (diff) | |
download | binutils-redhat-52d1d5dbfb8cca9a1c23bb7e2177c15587d67aed.tar.gz |
* gas/arm/copro.s: Avoid ldcl which encodes as a bad Neon instruction.
* gas/arm/copro.d: Update accordingly.
* gas/arm/neon-cond.s: New test. Conditional Neon opcodes in ARM mode.
* gas/arm/neon-cond.d: Expected results of above.
* gas/arm/neon-cov.s: New test. Coverage of Neon instructions.
* gas/arm/neon-cov.d: Expected results of above.
* gas/arm/neon-ldst-es.s: New test. Element and structure loads and
stores.
* gas/arm/neon-ldst-es.d: Expected results of above.
* gas/arm/neon-ldst-rm.s: New test. Single and multiple register loads
and stores.
* gas/arm/neon-ldst-rm.d: Expected results of above.
* gas/arm/neon-omit.s: New test. Omission of optional operands.
* gas/arm/neon-omit.d: Expected results of above.
* gas/arm/vfp1.d: Expect Neon syntax for some VFP instructions.
* gas/arm/vfp1_t2.d: Likewise.
* gas/arm/vfp1xD.d: Likewise.
* gas/arm/vfp1xD_t2.d: Likewise.
* gas/arm/vfp2.d: Likewise.
* gas/arm/vfp2_t2.d: Likewise.
* gas/arm/vfp3-32drs.s: New test. Extended D register range for VFP
instructions.
* gas/arm/vfp3-32drs.d: Expected results of above.
* gas/arm/vfp3-const-conv.s: New test. VFPv3 constant-load and
conversion instructions.
* gas/arm/vfp3-const-conv.d: Expected results of above.
Diffstat (limited to 'gas/testsuite/gas/arm/neon-ldst-rm.s')
-rw-r--r-- | gas/testsuite/gas/arm/neon-ldst-rm.s | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/gas/testsuite/gas/arm/neon-ldst-rm.s b/gas/testsuite/gas/arm/neon-ldst-rm.s new file mode 100644 index 0000000000..f9421ac556 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-ldst-rm.s @@ -0,0 +1,44 @@ +@ test register and multi-register loads and stores. + + .text + .arm + .syntax unified + + .macro multi op dir="" wb="" + \op\dir r2\wb,{d2} + \op\dir r2\wb,{d2-d3} + \op\dir r2\wb,{q2-q3} + \op\dir r2\wb,{q12-q14,q15} + \op\dir r2\wb,{d3,d4,d5-d8,d9,d10,d11,d12-d16,d17-d18} + .endm + + multi vldm + multi vldm ia + multi vldm ia "!" + multi vldm db "!" + + multi vstm + multi vstm ia + multi vstm ia "!" + multi vstm db "!" + +backward: + .word 500 + + .macro single op offset="" + \op d5,[r3] + \op d5,[r3,#-\offset] + \op d5,[r3,#\offset] + .endm + + vldr d22, forward + + single vldr 4 + single vstr 4 + single vldr 256 + single vstr 256 + +forward: + .word 700 + + vldr d7, backward |