diff options
| author | Richard Sandiford <rsandifo@nildram.co.uk> | 2004-05-07 16:39:26 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@nildram.co.uk> | 2004-05-07 16:39:26 +0000 |
| commit | d352292053185cee1ae4de85f1076a6f4f438556 (patch) | |
| tree | cb16ac1020e00887061ebd983b9f000cf6fefca1 /gas/testsuite/gas/mips/vr4120-2.s | |
| parent | 51ef188d4a4ba108e75b1a47c623b7a3942c5d3b (diff) | |
| download | binutils-redhat-d352292053185cee1ae4de85f1076a6f4f438556.tar.gz | |
* config/tc-mips.c (append_insn, mips_emit_delays): Extend -mfix-vr4120
to cope with VR4181A errata MD(1) and MD(4).
Diffstat (limited to 'gas/testsuite/gas/mips/vr4120-2.s')
| -rw-r--r-- | gas/testsuite/gas/mips/vr4120-2.s | 147 |
1 files changed, 147 insertions, 0 deletions
diff --git a/gas/testsuite/gas/mips/vr4120-2.s b/gas/testsuite/gas/mips/vr4120-2.s new file mode 100644 index 0000000000..1e5d606083 --- /dev/null +++ b/gas/testsuite/gas/mips/vr4120-2.s @@ -0,0 +1,147 @@ +# Test workarounds selected by -mfix-vr4120. +# Note that we only work around bugs gcc may generate. + +r21: + macc $4,$5,$6 + div $0,$7,$8 + or $4,$5 + + dmacc $4,$5,$6 + div $0,$7,$8 + or $4,$5 + + macc $4,$5,$6 + divu $0,$7,$8 + or $4,$5 + + dmacc $4,$5,$6 + divu $0,$7,$8 + or $4,$5 + + macc $4,$5,$6 + ddiv $0,$7,$8 + or $4,$5 + + dmacc $4,$5,$6 + ddiv $0,$7,$8 + or $4,$5 + + macc $4,$5,$6 + ddivu $0,$7,$8 + or $4,$5 + + dmacc $4,$5,$6 + ddivu $0,$7,$8 + or $4,$5 + +r23: + dmult $4,$5 + dmult $6,$7 + or $4,$5 + + dmultu $4,$5 + dmultu $6,$7 + or $4,$5 + + dmacc $4,$5,$6 + dmacc $6,$7,$8 + or $4,$5 + + dmult $4,$5 + dmacc $6,$7,$8 + or $4,$5 + +r24: + macc $4,$5,$6 + mtlo $7 + + dmacc $4,$5,$6 + mtlo $7 + + macc $4,$5,$6 + mthi $7 + + dmacc $4,$5,$6 + mthi $7 + +vr4181a_md1: + macc $4,$5,$6 + mult $4,$5 + or $4,$5 + + macc $4,$5,$6 + multu $4,$5 + or $4,$5 + + macc $4,$5,$6 + dmult $4,$5 + or $4,$5 + + macc $4,$5,$6 + dmultu $4,$5 + or $4,$5 + + dmacc $4,$5,$6 + mult $4,$5 + or $4,$5 + + dmacc $4,$5,$6 + multu $4,$5 + or $4,$5 + + dmacc $4,$5,$6 + dmult $4,$5 + or $4,$5 + + dmacc $4,$5,$6 + dmultu $4,$5 + or $4,$5 + +vr4181a_md4: + dmult $4,$5 + macc $4,$5,$6 + or $4,$5 + + dmultu $4,$5 + macc $4,$5,$6 + or $4,$5 + + div $0,$4,$5 + macc $4,$5,$6 + or $4,$5 + + divu $0,$4,$5 + macc $4,$5,$6 + or $4,$5 + + ddiv $0,$4,$5 + macc $4,$5,$6 + or $4,$5 + + ddivu $0,$4,$5 + macc $4,$5,$6 + or $4,$5 + + dmult $4,$5 + dmacc $4,$5,$6 + or $4,$5 + + dmultu $4,$5 + dmacc $4,$5,$6 + or $4,$5 + + div $0,$4,$5 + dmacc $4,$5,$6 + or $4,$5 + + divu $0,$4,$5 + dmacc $4,$5,$6 + or $4,$5 + + ddiv $0,$4,$5 + dmacc $4,$5,$6 + or $4,$5 + + ddivu $0,$4,$5 + dmacc $4,$5,$6 + or $4,$5 |