Rewrite SPU overlay handling code. Put overlay calls stubs in the

	overlays where possible.  Use a faster call stub, or optionally at
	compile time, a more compact stub.  Double size of _ovly_buf_table
	so that low bit of _ovly_table.buf can be used as a "present" bit.
	Reserve an extra _ovly_table entry for index zero.

3 files changed, 181 insertions, 127 deletions

diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index ec1018ee55..ed802deadf 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2008-01-28  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/ovl.d: Update.
+	* ld-spu/ovl2.d: Update.
+
 2008-01-26  Alan Modra  <amodra@bigpond.net.au>
 
 	* ld-elf/loadaddr.t: New, extracted from..
diff --git a/ld/testsuite/ld-spu/ovl.d b/ld/testsuite/ld-spu/ovl.d
index c6246594ba..0cd8788d14 100644
--- a/ld/testsuite/ld-spu/ovl.d
+++ b/ld/testsuite/ld-spu/ovl.d
@@ -7,65 +7,90 @@
 Disassembly of section \.text:
 
 00000100 <_start>:
- 100:	1c f8 00 81 	ai	\$1,\$1,-32
- 104:	48 20 00 00 	xor	\$0,\$0,\$0
- 108:	24 00 00 80 	stqd	\$0,0\(\$1\)
- 10c:	24 00 40 80 	stqd	\$0,16\(\$1\)
- 110:	33 00 04 00 	brsl	\$0,130 <00000000\.ovl_call\.f1_a1>	# 130
-			110: SPU_REL16	f1_a1
- 114:	33 00 04 80 	brsl	\$0,138 <00000000\.ovl_call\.f2_a1>	# 138
-			114: SPU_REL16	f2_a1
- 118:	33 00 07 00 	brsl	\$0,150 <00000000\.ovl_call\.f1_a2>	# 150
-			118: SPU_REL16	f1_a2
- 11c:	42 00 ac 09 	ila	\$9,344	# 158
-			11c: SPU_ADDR18	f2_a2
- 120:	35 20 04 80 	bisl	\$0,\$9
- 124:	1c 08 00 81 	ai	\$1,\$1,32	# 20
- 128:	32 7f fb 00 	br	100 <_start>	# 100
-			128: SPU_REL16	_start
+.*	ai	\$1,\$1,-32
+.*	xor	\$0,\$0,\$0
+.*	stqd	\$0,0\(\$1\)
+.*	stqd	\$0,16\(\$1\)
+.*	brsl	\$0,.* <00000000\.ovl_call\.f1_a1>.*
+.*SPU_REL16	f1_a1
+.*	brsl	\$0,.* <00000000\.ovl_call\.f2_a1>.*
+.*SPU_REL16	f2_a1
+.*	brsl	\$0,.* <00000000\.ovl_call\.f1_a2>.*
+.*SPU_REL16	f1_a2
+#.*	ila	\$9,328	# 148
+.*	ila	\$9,352	# 160
+.*SPU_ADDR18	f2_a2
+.*	bisl	\$0,\$9
+.*	ai	\$1,\$1,32	# 20
+.*	br	100 <_start>	# 100
+.*SPU_REL16	_start
 
 0000012c <f0>:
- 12c:	35 00 00 00 	bi	\$0
+.*	bi	\$0
+
+#00000130 <00000000\.ovl_call\.f1_a1>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 04 04 00.*
+#
+#00000138 <00000000\.ovl_call\.f2_a1>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 04 04 04.*
+#
+#00000140 <00000000\.ovl_call\.f1_a2>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 08 04 00.*
+#
+#00000148 <00000000\.ovl_call\.f2_a2>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 08 04 24.*
+#
+#00000150 <00000000\.ovl_call\.f4_a1>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 04 04 10.*
+#
+#00000158 <00000000.ovl_call.14:8>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 08 04 34.*
 
 00000130 <00000000\.ovl_call\.f1_a1>:
- 130:	42 02 00 4f 	ila	\$79,1024	# 400
- 134:	32 00 02 80 	br	148 .*
-			134: SPU_REL16	\*ABS\*\+0x148
-
-00000138 <00000000\.ovl_call\.f2_a1>:
- 138:	42 02 02 4f 	ila	\$79,1028	# 404
- 13c:	32 00 01 80 	br	148 .*
-			13c: SPU_REL16	\*ABS\*\+0x148
-
-00000140 <00000000\.ovl_call\.f4_a1>:
- 140:	42 02 08 4f 	ila	\$79,1040	# 410
- 144:	40 20 00 00 	nop	\$0
- 148:	42 00 00 ce 	ila	\$78,1
- 14c:	32 00 0a 80 	br	1a0 <__ovly_load>	# 1a0
-			14c: SPU_REL16	__ovly_load
-
-00000150 <00000000\.ovl_call\.f1_a2>:
- 150:	42 02 00 4f 	ila	\$79,1024	# 400
- 154:	32 00 02 80 	br	168 .*
-			154: SPU_REL16	\*ABS\*\+0x168
-
-00000158 <00000000\.ovl_call\.f2_a2>:
- 158:	42 02 12 4f 	ila	\$79,1060	# 424
- 15c:	32 00 01 80 	br	168 .*
-			15c: SPU_REL16	\*ABS\*\+0x168
-
-00000160 <00000000\.ovl_call\.14:8>:
- 160:	42 02 1a 4f 	ila	\$79,1076	# 434
- 164:	40 20 00 00 	nop	\$0
- 168:	42 00 01 4e 	ila	\$78,2
- 16c:	32 00 06 80 	br	1a0 <__ovly_load>	# 1a0
-			16c: SPU_REL16	__ovly_load
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1024	# 400
+.*	br	.* <__ovly_load>.*
+
+00000140 <00000000\.ovl_call\.f2_a1>:
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1028	# 404
+.*	br	.* <__ovly_load>.*
+
+00000150 <00000000.ovl_call.f1_a2>:
+.*	ila	\$78,2
+.*	lnop
+.*	ila	\$79,1024	# 400
+.*	br	.* <__ovly_load>.*
+
+00000160 <00000000\.ovl_call\.f2_a2>:
+.*	ila	\$78,2
+.*	lnop
+.*	ila	\$79,1060	# 424
+.*	br	.* <__ovly_load>.*
+
+00000170 <00000000\.ovl_call\.f4_a1>:
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1040	# 410
+.*	br	.* <__ovly_load>.*
+
+00000180 <00000000.ovl_call.14:8>:
+.*	ila	\$78,2
+.*	lnop
+.*	ila	\$79,1076	# 434
+.*	br	.* <__ovly_load>.*
+
 #...
 [0-9a-f]+ <__ovly_return>:
-[0-9a-f ]+:	3f e1 00 4e 	shlqbyi	\$78,\$0,4
-[0-9a-f ]+:	3f e2 00 4f 	shlqbyi	\$79,\$0,8
-[0-9a-f ]+:	25 00 27 ce 	biz	\$78,\$79
-
+#...
 [0-9a-f]+ <__ovly_load>:
 #...
 [0-9a-f]+ <_ovly_debug_event>:
@@ -73,67 +98,75 @@ Disassembly of section \.text:
 Disassembly of section \.ov_a1:
 
 00000400 <f1_a1>:
- 400:	32 00 01 80 	br	40c <f3_a1>	# 40c
-			400: SPU_REL16	f3_a1
+.*	br	.* <f3_a1>.*
+.*SPU_REL16	f3_a1
 
 00000404 <f2_a1>:
- 404:	42 00 a0 03 	ila	\$3,320	# 140
-			404: SPU_ADDR18	f4_a1
- 408:	35 00 00 00 	bi	\$0
+#.*	ila	\$3,336	# 150
+.*	ila	\$3,368	# 170
+.*SPU_ADDR18	f4_a1
+.*	bi	\$0
 
 0000040c <f3_a1>:
- 40c:	35 00 00 00 	bi	\$0
+.*	bi	\$0
 
 00000410 <f4_a1>:
- 410:	35 00 00 00 	bi	\$0
+.*	bi	\$0
 	\.\.\.
 Disassembly of section \.ov_a2:
 
 00000400 <f1_a2>:
- 400:	24 00 40 80 	stqd	\$0,16\(\$1\)
- 404:	24 ff 80 81 	stqd	\$1,-32\(\$1\)
- 408:	1c f8 00 81 	ai	\$1,\$1,-32
- 40c:	33 7f a4 00 	brsl	\$0,12c <f0>	# 12c
-			40c: SPU_REL16	f0
- 410:	33 7f a4 00 	brsl	\$0,130 <00000000\.ovl_call\.f1_a1>	# 130
-			410: SPU_REL16	f1_a1
- 414:	33 00 03 80 	brsl	\$0,430 <f3_a2>	# 430
-			414: SPU_REL16	f3_a2
- 418:	34 00 c0 80 	lqd	\$0,48\(\$1\)	# 30
- 41c:	1c 08 00 81 	ai	\$1,\$1,32	# 20
- 420:	35 00 00 00 	bi	\$0
+.*	stqd	\$0,16\(\$1\)
+.*	stqd	\$1,-32\(\$1\)
+.*	ai	\$1,\$1,-32
+.*	brsl	\$0,12c <f0>	# 12c
+.*SPU_REL16	f0
+.*	brsl	\$0,130 <00000000\.ovl_call\.f1_a1>	# 130
+.*SPU_REL16	f1_a1
+.*	brsl	\$0,430 <f3_a2>	# 430
+.*SPU_REL16	f3_a2
+.*	lqd	\$0,48\(\$1\)	# 30
+.*	ai	\$1,\$1,32	# 20
+.*	bi	\$0
 
 00000424 <f2_a2>:
- 424:	41 00 00 03 	ilhu	\$3,0
-			424: SPU_ADDR16_HI	f4_a2
- 428:	60 80 b0 03 	iohl	\$3,352	# 160
-			428: SPU_ADDR16_LO	f4_a2
- 42c:	35 00 00 00 	bi	\$0
+.*	ilhu	\$3,0
+.*SPU_ADDR16_HI	f4_a2
+#.*	iohl	\$3,344	# 158
+.*	iohl	\$3,384	# 180
+.*SPU_ADDR16_LO	f4_a2
+.*	bi	\$0
 
 00000430 <f3_a2>:
- 430:	35 00 00 00 	bi	\$0
+.*	bi	\$0
 
 00000434 <f4_a2>:
- 434:	32 7f ff 80 	br	430 <f3_a2>	# 430
-			434: SPU_REL16	f3_a2
+.*	br	.* <f3_a2>.*
+.*SPU_REL16	f3_a2
 	\.\.\.
 Disassembly of section .data:
 
-00000440 <_ovly_table>:
- 440:	00 00 04 00 .*
- 444:	00 00 00 20 .*
- 448:	00 00 02 f0 .*
+00000440 <_ovly_table-0x10>:
+	\.\.\.
  44c:	00 00 00 01 .*
+00000450 <_ovly_table>:
  450:	00 00 04 00 .*
- 454:	00 00 00 40 .*
- 458:	00 00 03 10 .*
- 45c:	00 00 00 01 .*
+ 454:	00 00 00 20 .*
+# 458:	00 00 03 40 .*
+ 458:	00 00 03 70 .*
+ 45c:	00 00 00 02 .*
+ 460:	00 00 04 00 .*
+ 464:	00 00 00 40 .*
+# 468:	00 00 03 60 .*
+ 468:	00 00 03 90 .*
+ 46c:	00 00 00 02 .*
+
+00000470 <_ovly_buf_table>:
+	\.\.\.
 
-00000460 <_ovly_buf_table>:
- 460:	00 00 00 00 .*
 Disassembly of section \.toe:
 
-00000470 <_EAR_>:
+00000480 <_EAR_>:
 	\.\.\.
 Disassembly of section \.note\.spu_name:
 
diff --git a/ld/testsuite/ld-spu/ovl2.d b/ld/testsuite/ld-spu/ovl2.d
index bf62e0364f..1cd1d33968 100644
--- a/ld/testsuite/ld-spu/ovl2.d
+++ b/ld/testsuite/ld-spu/ovl2.d
@@ -7,40 +7,50 @@
 Disassembly of section \.text:
 
 00000100 <_start>:
- 100:	33 00 06 00 	brsl	\$0,130 <00000000\.ovl_call\.f1_a1>	# 130
-			100: SPU_REL16	f1_a1
- 104:	33 00 03 80 	brsl	\$0,120 <00000000\.ovl_call\.10:4>	# 120
-			104: SPU_REL16	setjmp
- 108:	32 7f ff 00 	br	100 <_start>	# 100
-			108: SPU_REL16	_start
+.*	brsl	\$0,.* <00000000\.ovl_call\.f1_a1>.*
+.*SPU_REL16	f1_a1
+.*	brsl	\$0,.* <00000000\.ovl_call\.10:4>.*
+.*SPU_REL16	setjmp
+.*	br	100 <_start>	# 100
+.*SPU_REL16	_start
 
 0000010c <setjmp>:
- 10c:	35 00 00 00 	bi	\$0
+.*	bi	\$0
 
 00000110 <longjmp>:
- 110:	35 00 00 00 	bi	\$0
-	...
-
-00000120 <00000000\.ovl_call.10:4>:
- 120:	42 00 86 4f 	ila	\$79,268	# 10c
- 124:	40 20 00 00 	nop	\$0
- 128:	42 00 00 4e 	ila	\$78,0
- 12c:	32 00 0a 80 	br	180 <__ovly_load>	# 180
-			12c: SPU_REL16	__ovly_load
-
-00000130 <00000000\.ovl_call.f1_a1>:
- 130:	42 02 00 4f 	ila	\$79,1024	# 400
- 134:	40 20 00 00 	nop	\$0
- 138:	42 00 00 ce 	ila	\$78,1
- 13c:	32 00 08 80 	br	180 <__ovly_load>	# 180
-			13c: SPU_REL16	__ovly_load
+.*	bi	\$0
+.*
+
+#00000118 <00000000\.ovl_call.f1_a1>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 04 04 00.*
+#
+#00000120 <00000000\.ovl_call.10:4>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 00 01 0c.*
+#
+#00000128 <_SPUEAR_f1_a2>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 08 04 00.*
+
+00000120 <00000000\.ovl_call.f1_a1>:
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1024	# 400
+.*	br	.* <__ovly_load>.*
+
+00000130 <00000000\.ovl_call.10:4>:
+.*	ila	\$78,0
+.*	lnop
+.*	ila	\$79,268	# 10c
+.*	br	.* <__ovly_load>.*
 
 00000140 <_SPUEAR_f1_a2>:
- 140:	42 02 00 4f 	ila	\$79,1024	# 400
- 144:	40 20 00 00 	nop	\$0
- 148:	42 00 01 4e 	ila	\$78,2
- 14c:	32 00 06 80 	br	180 <__ovly_load>	# 180
-			14c: SPU_REL16	__ovly_load
+.*	ila	\$78,2
+.*	lnop
+.*	ila	\$79,1024	# 400
+.*	br	.* <__ovly_load>.*
+
 #...
 Disassembly of section \.ov_a1:
 
@@ -55,21 +65,27 @@ Disassembly of section \.ov_a2:
 	\.\.\.
 Disassembly of section \.data:
 
-00000410 <_ovly_table>:
- 410:	00 00 04 00 	.*
- 414:	00 00 00 10 	.*
- 418:	00 00 02 d0 	.*
+00000410 <_ovly_table-0x10>:
+	\.\.\.
  41c:	00 00 00 01 	.*
+00000420 <_ovly_table>:
  420:	00 00 04 00 	.*
  424:	00 00 00 10 	.*
- 428:	00 00 02 e0 	.*
- 42c:	00 00 00 01 	.*
+# 428:	00 00 03 10 	.*
+ 428:	00 00 03 30 	.*
+ 42c:	00 00 00 02 	.*
+ 430:	00 00 04 00 	.*
+ 434:	00 00 00 10 	.*
+# 438:	00 00 03 20 	.*
+ 438:	00 00 03 40 	.*
+ 43c:	00 00 00 02 	.*
+
+00000440 <_ovly_buf_table>:
+	\.\.\.
 
-00000430 <_ovly_buf_table>:
- 430:	00 00 00 00 	.*
 Disassembly of section \.toe:
 
-00000440 <_EAR_>:
+00000450 <_EAR_>:
 	\.\.\.
 Disassembly of section \.note\.spu_name: