Support AVX Programming Reference (June, 2010)

gas/

2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd
	and .f16c.

	* doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c.

gas/testsuite/

2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* gas/i386/arch-10.s: Add xsaveopt.
	* gas/i386/x86-64-arch-2.s: Likwise.

	* gas/i386/arch-10.d: Updated.
	* gas/i386/arch-10-1.l: Likewise.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/x86-64-arch-2.d: Likewise.

	* gas/i386/f16c-intel.d: New.
	* gas/i386/f16c.d: Likewise.
	* gas/i386/f16c.s: Likewise.
	* gas/i386/fsgs-intel.d: Likewise.
	* gas/i386/fsgs.d: Likewise.
	* gas/i386/fsgs.s: Likewise.
	* gas/i386/rdrnd-intel.d: Likewise.
	* gas/i386/rdrnd.d: Likewise.
	* gas/i386/rdrnd.s: Likewise.
	* gas/i386/x86-64-f16c-intel.d: Likewise.
	* gas/i386/x86-64-f16c.d: Likewise.
	* gas/i386/x86-64-f16c.s: Likewise.
	* gas/i386/x86-64-fsgs-intel.d: Likewise.
	* gas/i386/x86-64-fsgs.d: Likewise.
	* gas/i386/x86-64-fsgs.s: Likewise.
	* gas/i386/x86-64-rdrnd-intel.d: Likewise.
	* gas/i386/x86-64-rdrnd.d: Likewise.
	* gas/i386/x86-64-rdrnd.s: Likewise.

	* gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel,
	rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs,
	x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel.

	* gas/i386/x86-64-xsave.s: Add tests for xsaveopt64.

	* gas/i386/x86-64-xsave-intel.d: Updated.
	* gas/i386/x86-64-xsave.d: Likewise.

opcodes/

2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* i386-dis.c (PREFIX_0FAE_REG_0): New.
	(PREFIX_0FAE_REG_1): Likewise.
	(PREFIX_0FAE_REG_2): Likewise.
	(PREFIX_0FAE_REG_3): Likewise.
	(PREFIX_VEX_3813): Likewise.
	(PREFIX_VEX_3A1D): Likewise.
	(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
	PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
	PREFIX_VEX_3A1D.
	(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
	(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
	PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.

	* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
	CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
	(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.

	* i386-opc.h (CpuXsaveopt): New.
	(CpuFSGSBase):Likewise.
	(CpuRdRnd): Likewise.
	(CpuF16C): Likewise.
	(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
	cpuf16c.

	* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
	wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.

1 files changed, 52 insertions, 3 deletions

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index ecd8cca2a2..224540e1a8 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -741,6 +741,10 @@ enum
   PREFIX_0F7D,
   PREFIX_0F7E,
   PREFIX_0F7F,
+  PREFIX_0FAE_REG_0,
+  PREFIX_0FAE_REG_1,
+  PREFIX_0FAE_REG_2,
+  PREFIX_0FAE_REG_3,
   PREFIX_0FB8,
   PREFIX_0FBD,
   PREFIX_0FC2,
@@ -936,6 +940,7 @@ enum
   PREFIX_VEX_380D,
   PREFIX_VEX_380E,
   PREFIX_VEX_380F,
+  PREFIX_VEX_3813,
   PREFIX_VEX_3817,
   PREFIX_VEX_3818,
   PREFIX_VEX_3819,
@@ -1026,6 +1031,7 @@ enum
   PREFIX_VEX_3A17,
   PREFIX_VEX_3A18,
   PREFIX_VEX_3A19,
+  PREFIX_VEX_3A1D,
   PREFIX_VEX_3A20,
   PREFIX_VEX_3A21,
   PREFIX_VEX_3A22,
@@ -3033,6 +3039,30 @@ static const struct dis386 prefix_table[][4] = {
     { "movdqa",	{ EXxS, XM } },
   },
 
+  /* PREFIX_0FAE_REG_0 */
+  {
+    { Bad_Opcode },
+    { "rdfsbase", { Ev } },
+  },
+
+  /* PREFIX_0FAE_REG_1 */
+  {
+    { Bad_Opcode },
+    { "rdgsbase", { Ev } },
+  },
+
+  /* PREFIX_0FAE_REG_2 */
+  {
+    { Bad_Opcode },
+    { "wrfsbase", { Ev } },
+  },
+
+  /* PREFIX_0FAE_REG_3 */
+  {
+    { Bad_Opcode },
+    { "wrgsbase", { Ev } },
+  },
+
   /* PREFIX_0FB8 */
   {
     { Bad_Opcode },
@@ -4419,6 +4449,13 @@ static const struct dis386 prefix_table[][4] = {
     { VEX_W_TABLE (VEX_W_380F_P_2) },
   },
 
+  /* PREFIX_VEX_3813 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vcvtph2ps", { XM, EXxmmq } },
+  },
+
   /* PREFIX_VEX_3817 */
   {
     { Bad_Opcode },
@@ -5050,6 +5087,13 @@ static const struct dis386 prefix_table[][4] = {
     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
   },
 
+  /* PREFIX_VEX_3A1D */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vcvtps2ph", { EXxmmq, XM, Ib } },
+  },
+
   /* PREFIX_VEX_3A20 */
   {
     { Bad_Opcode },
@@ -7533,7 +7577,7 @@ static const struct dis386 vex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_3813) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ -7835,7 +7879,7 @@ static const struct dis386 vex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_3A1D) },
     { Bad_Opcode },
     { Bad_Opcode },
     /* 20 */
@@ -10355,18 +10399,22 @@ static const struct dis386 mod_table[][2] = {
   {
     /* MOD_0FAE_REG_0 */
     { "fxsave",		{ FXSAVE } },
+    { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
   },
   {
     /* MOD_0FAE_REG_1 */
     { "fxrstor",	{ FXSAVE } },
+    { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
   },
   {
     /* MOD_0FAE_REG_2 */
     { "ldmxcsr",	{ Md } },
+    { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
   },
   {
     /* MOD_0FAE_REG_3 */
     { "stmxcsr",	{ Md } },
+    { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
   },
   {
     /* MOD_0FAE_REG_4 */
@@ -10379,7 +10427,7 @@ static const struct dis386 mod_table[][2] = {
   },
   {
     /* MOD_0FAE_REG_6 */
-    { Bad_Opcode },
+    { "xsaveopt",	{ FXSAVE } },
     { RM_TABLE (RM_0FAE_REG_6) },
   },
   {
@@ -10402,6 +10450,7 @@ static const struct dis386 mod_table[][2] = {
   {
     /* MOD_0FC7_REG_6 */
     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
+    { "rdrnd",		{ Ev } },
   },
   {
     /* MOD_0FC7_REG_7 */