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| author | H.J. Lu <hjl@lucon.org> | 2007-05-01 12:59:24 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@lucon.org> | 2007-05-01 12:59:24 +0000 |
| commit | 2a786e9e6ae905dc6eebf4357b83552b2448f1cc (patch) | |
| tree | c32e9bd0d8f28ba59e9d2262a4fb8461ae4ffa8f /opcodes/i386-opc.c | |
| parent | b3bdd229a16fe199d50bb5df84defd801dda7a96 (diff) | |
| download | binutils-redhat-2a786e9e6ae905dc6eebf4357b83552b2448f1cc.tar.gz | |
gas/config/
2007-05-01 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_template): Check suffix for crc32 in
Intel mdoe.
(process_suffix): Default the suffix of 8bit crc32 to
BYTE_MNEM_SUFFIX.
(check_byte_reg): Skip check for 8bit crc32.
gas/testsuite/
2007-05-01 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/crc32-intel.d: New file.
* gas/i386/crc32.d:Likewise.
* gas/i386/crc32.s:Likewise.
* gas/i386/x86-64-crc32-intel.d:Likewise.
* gas/i386/x86-64-crc32.d:Likewise.
* gas/i386/x86-64-crc32.s:Likewise.
* gas/i386/i386.exp: Run crc32, crc32-intel, x86-64-crc32
and x86-64-crc32-intel.
opcodes/
2007-05-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (CRC32_Fixup): Properly handle Intel mode and
check data size prefix in 16bit mode.
* i386-opc.c (i386_optab): Default crc32 to non-8bit and
support Intel mode.
Diffstat (limited to 'opcodes/i386-opc.c')
| -rw-r--r-- | opcodes/i386-opc.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/opcodes/i386-opc.c b/opcodes/i386-opc.c index a374b654e3..e03152cca1 100644 --- a/opcodes/i386-opc.c +++ b/opcodes/i386-opc.c @@ -1442,10 +1442,12 @@ const template i386_optab[] = {"pcmpestrm", 3, 0x660f3a60,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, {"pcmpistri", 3, 0x660f3a63,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, {"pcmpistrm", 3, 0x660f3a62,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"crc32b", 2, 0xf20f38f0,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Reg8|ByteMem, Reg32|Reg64, 0 } }, -{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Reg8, Reg32|Reg64, 0 } }, +/* We put non-8bit version before 8bit so that crc32 with memory operand + defaults to non-8bit. */ {"crc32", 2, 0xf20f38f1,X, CpuSSE4_2, wl_Suf|Modrm, { WordReg|WordMem, Reg32, 0 } }, {"crc32", 2, 0xf20f38f1,X, CpuSSE4_2|Cpu64, q_Suf|IgnoreSize|Modrm|Rex64, { Reg64|LLongMem, Reg64, 0 } }, +{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2, b_Suf|Modrm, { Reg8|ByteMem, Reg32, 0 } }, +{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2|Cpu64, b_Suf|IgnoreSize|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0 } }, /* AMD 3DNow! instructions. */ |