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authorH.J. Lu <hjl@lucon.org>2009-09-24 16:37:09 +0000
committerH.J. Lu <hjl@lucon.org>2009-09-24 16:37:09 +0000
commit7361039029da921bac5bb0f4082e818da496b233 (patch)
tree81fe7d0104eff1d4b3419b6cee88e56067db7517 /opcodes/i386-opc.h
parent249dbd0a1eb89b6848d40b0c77f872a11f34033b (diff)
downloadbinutils-redhat-7361039029da921bac5bb0f4082e818da496b233.tar.gz
gas/
2009-09-24 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Check vex == 2 instead of vex256. opcodes/ 2009-09-24 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove Vex256. (set_bitfield): Handle XXX=V. * i386-opc.h (Vex): Update comments. (Vex256): Removed. (VexNDS): Updated. (i386_opcode_modifier): Change vex to 2 bits. Remove vex256. * i386-opc.tbl: Replace "Vex|Vex256" with Vex=2. * i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-opc.h')
-rw-r--r--opcodes/i386-opc.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 2dd8eeda66..df71da758a 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -257,14 +257,15 @@ typedef union i386_cpu_flags
#define Rex64 (NoRex64 + 1)
/* deprecated fp insn, gets a warning */
#define Ugh (Rex64 + 1)
-/* insn has VEX prefix. */
+/* insn has VEX prefix:
+ 1: 128bit VEX prefix.
+ 2: 256bit VEX prefix.
+ */
#define Vex (Ugh + 1)
-/* insn has 256bit VEX prefix. */
-#define Vex256 (Vex + 1)
/* insn has VEX NDS. Register-only source is encoded in Vex prefix.
We use VexNDS on insns with VEX DDS since the register-only source
is the second source register. */
-#define VexNDS (Vex256 + 1)
+#define VexNDS (Vex + 1)
/* insn has VEX NDD. Register destination is encoded in Vex
prefix. */
#define VexNDD (VexNDS + 1)
@@ -336,8 +337,7 @@ typedef struct i386_opcode_modifier
unsigned int norex64:1;
unsigned int rex64:1;
unsigned int ugh:1;
- unsigned int vex:1;
- unsigned int vex256:1;
+ unsigned int vex:2;
unsigned int vexnds:1;
unsigned int vexndd:1;
unsigned int vexw0:1;