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| author | Roland McGrath <roland@gnu.org> | 2012-06-22 16:41:59 +0000 |
|---|---|---|
| committer | Roland McGrath <roland@gnu.org> | 2012-06-22 16:41:59 +0000 |
| commit | fb972bd7aecfb5e6c66d1e7f26ea3bd6dd21689a (patch) | |
| tree | f2f516a6f1c20bac14e567191bd123335f9abc52 /opcodes/i386-opc.h | |
| parent | f2b713c3c408c62776383c083c9e06d6565fec5b (diff) | |
| download | binutils-redhat-fb972bd7aecfb5e6c66d1e7f26ea3bd6dd21689a.tar.gz | |
gas/
* config/tc-i386.c (parse_insn): Don't complain about REP prefix
when the template has opcode_modifier.repprefixok set.
* NEWS: Mention the change.
gas/testsuite/
* gas/i386/rep-bsf.d: New file.
* gas/i386/rep-bsf.s: New file.
* gas/i386/i386.exp: Add the new test.
opcodes/
* i386-opc.h (RepPrefixOk): New enum constant.
(i386_opcode_modifier): New bitfield 'repprefixok'.
* i386-gen.c (opcode_modifiers): Add RepPrefixOk.
* i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
instructions that have IsString.
* i386-tbl.h: Regenerate.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index f130a96ce8..96bdfb54ea 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -1,5 +1,5 @@ /* Declarations for Intel 80386 opcode table - Copyright 2007, 2008, 2009, 2010 + Copyright 2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -309,6 +309,8 @@ enum #define HLEPrefixAny 2 #define HLEPrefixRelease 3 HLEPrefixOk, + /* An instruction on which a "rep" prefix is acceptable. */ + RepPrefixOk, /* Convert to DWORD */ ToDword, /* Convert to QWORD */ @@ -338,7 +340,7 @@ enum 0: VEX.vvvv must be 1111b. 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where the content of source registers will be preserved. - VEX.DDS. The second register operand is encoded in VEX.vvvv + VEX.DDS. The second register operand is encoded in VEX.vvvv where the content of first source register will be overwritten by the result. VEX.NDD2. The second destination register operand is encoded in @@ -443,6 +445,7 @@ typedef struct i386_opcode_modifier unsigned int firstxmm0:1; unsigned int implicit1stxmm0:1; unsigned int hleprefixok:2; + unsigned int repprefixok:1; unsigned int todword:1; unsigned int toqword:1; unsigned int addrprefixop0:1; @@ -662,7 +665,7 @@ typedef struct insn_template /* extension_opcode is the 3 bit extension for group <n> insns. This field is also used to store the 8-bit opcode suffix for the AMD 3DNow! instructions. - If this template has no extension opcode (the usual case) use None + If this template has no extension opcode (the usual case) use None Instructions */ unsigned int extension_opcode; #define None 0xffff /* If no extension_opcode is possible. */ |