diff options
| author | spop <spop> | 2009-11-18 20:28:57 +0000 |
|---|---|---|
| committer | spop <spop> | 2009-11-18 20:28:57 +0000 |
| commit | a5dba0ce16d25524ba81829c321dd44d72ae3574 (patch) | |
| tree | ce880678a813cb8efbef4ba0f051f35aec3d8aaa /opcodes/i386-opc.tbl | |
| parent | 61029f03689295e346e5124c4a3aa6248f465c5a (diff) | |
| download | binutils-redhat-a5dba0ce16d25524ba81829c321dd44d72ae3574.tar.gz | |
2009-11-18 Sebastian Pop <sebastian.pop@amd.com>
gas/
* config/tc-i386.c (cpu_arch): Remove cvt16.
(md_show_usage): Same.
* doc/c-i386.texi: Same.
gas/testsuite/
* gas/i386/cvt16.d: Removed.
* gas/i386/cvt16.s: Removed.
* gas/i386/x86-64-cvt16.d: Removed.
* gas/i386/x86-64-cvt16.s: Removed.
* gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests.
opcodes/
* i386-dis.c (VEX_LEN_XOP_08_A0): Removed.
(VEX_LEN_XOP_08_A1): Removed.
(xop_table): Remove entries for VEX_LEN_XOP_08_A0 and
VEX_LEN_XOP_08_A1.
(vex_len_table): Same.
* i386-gen.c (CPU_CVT16_FLAGS): Removed.
(cpu_flags): Remove field for CpuCVT16.
* i386-opc.h (CpuCVT16): Removed.
(i386_cpu_flags): Remove bitfield cpucvt16.
(i386-opc.tbl): Remove CVT16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index c9bf4212d2..687dc93807 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2548,13 +2548,6 @@ vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sourc vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -// CVT16 instructions - -vcvtph2ps, 3, 0xa0, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } -vcvtph2ps, 3, 0xa0, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM } -vcvtps2ph, 3, 0xa1, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, RegXMM, Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex } -vcvtps2ph, 3, 0xa1, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Imm8, RegYMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex } - // XOP instructions vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } |