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| author | H.J. Lu <hjl@lucon.org> | 2007-11-14 22:31:54 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@lucon.org> | 2007-11-14 22:31:54 +0000 |
| commit | e600a720aa9559c71161715354f4ff6912818348 (patch) | |
| tree | 5217292e071d6f8f0f7af1307a5feaa24536b714 /opcodes/ia64-ic.tbl | |
| parent | 36bc3cf46fa3e821908c019b270c77a665927769 (diff) | |
| download | binutils-redhat-e600a720aa9559c71161715354f4ff6912818348.tar.gz | |
gas/
2007-11-14 Tristan Gingold <gingold@adacore.com>
* config/tc-ia64.c (AR_RUC): Defined.
(ar): Add "ar.ruc".
(specify_resource): Handle AR_RUC like AR_ITC.
gas/testsuite/
2007-11-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/ia64/dv-raw-err.s: Add tests for ar.ruc.
* gas/ia64/dv-waw-err.s: Likewise.
* gas/ia64/invalid-ar.s: Likewise.
* gas/ia64/regs.s: Add tests for ar.ruc and ar44.
* gas/ia64/dv-raw-err.l: Updated.
* gas/ia64/dv-waw-err.l: Likewise.
* gas/ia64/invalid-ar.l: Likewise.
* gas/ia64/regs.d: Likewise.
opcodes/
2007-11-14 H.J. Lu <hongjiu.lu@intel.com>
* ia64-ic.tbl: Updated for Itanium 9100 series.
* ia64-raw.tbl: Likewise.
* ia64-waw.tbl: Likewise.
* ia64-asmtab.c: Regenerated.
2007-11-14 Tristan Gingold <gingold@adacore.com>
* ia64-dis.c (print_insn_ia64): Handle ar.ruc.
* ia64-gen.c (lookup_regindex): Likewise.
Diffstat (limited to 'opcodes/ia64-ic.tbl')
| -rw-r--r-- | opcodes/ia64-ic.tbl | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/opcodes/ia64-ic.tbl b/opcodes/ia64-ic.tbl index 8877ad0104..1bbd07f205 100644 --- a/opcodes/ia64-ic.tbl +++ b/opcodes/ia64-ic.tbl @@ -90,6 +90,7 @@ mov-from-AR-M; mov_ar[Format in {M31}] mov-from-AR-PFS; IC:mov-from-AR-I[Field(ar3) == PFS] mov-from-AR-RNAT; IC:mov-from-AR-M[Field(ar3) == RNAT] mov-from-AR-RSC; IC:mov-from-AR-M[Field(ar3) == RSC] +mov-from-AR-RUC; IC:mov-from-AR-M[Field(ar3) == RUC] mov-from-AR-rv; IC:none mov-from-AR-SSD; IC:mov-from-AR-M[Field(ar3) == SSD] mov-from-AR-UNAT; IC:mov-from-AR-M[Field(ar3) == UNAT] @@ -158,6 +159,7 @@ mov-to-AR-M; mov_ar[Format in {M29 M30}] mov-to-AR-PFS; IC:mov-to-AR-I[Field(ar3) == PFS] mov-to-AR-RNAT; IC:mov-to-AR-M[Field(ar3) == RNAT] mov-to-AR-RSC; IC:mov-to-AR-M[Field(ar3) == RSC] +mov-to-AR-RUC; IC:mov-to-AR-M[Field(ar3) == RUC] mov-to-AR-SSD; IC:mov-to-AR-M[Field(ar3) == SSD] mov-to-AR-UNAT; IC:mov-to-AR-M[Field(ar3) == UNAT] mov-to-BR; mov_br[Format in {I21}] |