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authorH.J. Lu <hjl.tools@gmail.com>2012-09-04 13:52:04 +0000
committerH.J. Lu <hjl.tools@gmail.com>2012-09-04 13:52:04 +0000
commitcb1c35684d293119560d60cf00f515f4db09e481 (patch)
treef46ff69201517f79f4cd7d830ef09adac8ca0f62 /opcodes/ia64-waw.tbl
parentd0704435a1cb729119c23ab075d55596d12f0504 (diff)
downloadbinutils-redhat-cb1c35684d293119560d60cf00f515f4db09e481.tar.gz
Add Intel Itanium Series 9500 support
bfd/ 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> * cpu-ia64-opc.c (ins_cnt6a): New function. (ext_cnt6a): Ditto. (ins_strd5b): Ditto. (ext_strd5b): Ditto. (elf64_ia64_operands): Add new operand types. gas/ 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> * config/tc-ia64.c (reg_symbol): Add a new register. (indirect_reg): Ditto. (pseudo_func): Add new symbolic constants. (operand_match): Add new operand types recognition. (operand_insn): Add new register recognition. (md_begin): Add new register definition. (specify_resource): Add new register recognition. gas/testsuite/ 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> * gas/testsuite/gas/ia64/psn.d: New file. * gas/testsuite/gas/ia64/psn.s: New file. * gas/testsuite/gas/ia64/ia64.exp: Add new testcase. * gas/testsuite/gas/ia64/opc-i.d: Fixed failing tests. * gas/testsuite/gas/ia64/opc-m.d: Ditto. include/opcode/ 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> * ia64.h (ia64_opnd): Add new operand types. opcodes/ 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> * ia64-asmtab.h (completer_index): Extend bitfield to full uint. * ia64-gen.c: Promote completer index type to longlong. (irf_operand): Add new register recognition. (in_iclass_mov_x): Add an entry for the new mov_* instruction type. (lookup_specifier): Add new resource recognition. (insert_bit_table_ent): Relax abort condition according to the changed completer index type. (print_dis_table): Fix printf format for completer index. * ia64-ic.tbl: Add a new instruction class. * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions. * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions. * ia64-opc.h: Define short names for new operand types. * ia64-raw.tbl: Add new RAW resource for DAHR register. * ia64-waw.tbl: Add new WAW resource for DAHR register. * ia64-asmtab.c: Regenerate.
Diffstat (limited to 'opcodes/ia64-waw.tbl')
-rw-r--r--opcodes/ia64-waw.tbl1
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/ia64-waw.tbl b/opcodes/ia64-waw.tbl
index 82b9e839a5..44efaa8314 100644
--- a/opcodes/ia64-waw.tbl
+++ b/opcodes/ia64-waw.tbl
@@ -67,6 +67,7 @@ CR[PMV]; IC:mov-to-CR-PMV; IC:mov-to-CR-PMV; impliedF
CR[PTA]; IC:mov-to-CR-PTA; IC:mov-to-CR-PTA; impliedF
CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-CR-TPR; impliedF
CR%, % in 3-7, 10-15, 18, 28-63, 75-79, 82-127; IC:none; IC:none; none
+DAHR%, % in 0-7; IC:br.call, brl.call, br.ret, IC:mov-to-AR-BSPSTORE, IC:mov-to-DAHR, rfi; IC:br.call, brl.call, br.ret, IC:mov-to-AR-BSPSTORE, IC:mov-to-DAHR, rfi; implied
DBR#; IC:mov-to-IND-DBR+3; IC:mov-to-IND-DBR+3; impliedF
DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none
DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF