* m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20,

mem20): New.
(src16-16-20-An-relative-*): New.
(dst16-*-20-An-relative-*): New.
(dst16-16-16sa-*): New
(dst16-16-16ar-*): New
(dst32-16-16sa-Unprefixed-*): New
(jsri): Fix operands.
(setzx): Fix encoding.

* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.h: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.

1 files changed, 95 insertions, 52 deletions

diff --git a/opcodes/m32c-desc.c b/opcodes/m32c-desc.c
index c87ddc7631..74c9d40f09 100644
--- a/opcodes/m32c-desc.c
+++ b/opcodes/m32c-desc.c
@@ -916,8 +916,10 @@ const CGEN_IFLD m32c_cgen_ifld_table[] =
   { M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
   { M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
   { M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
+  { M32C_F_DSP_40_U20, "f-dsp-40-u20", 32, 32, 8, 20, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
   { M32C_F_DSP_40_U24, "f-dsp-40-u24", 32, 32, 8, 24, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
   { M32C_F_DSP_40_S32, "f-dsp-40-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
+  { M32C_F_DSP_48_U20, "f-dsp-48-u20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
   { M32C_F_DSP_48_U24, "f-dsp-48-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
   { M32C_F_DSP_16_S32, "f-dsp-16-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
   { M32C_F_DSP_24_S32, "f-dsp-24-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
@@ -968,6 +970,7 @@ const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U20_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [];
 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [];
@@ -1028,6 +1031,12 @@ const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [] =
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
     { 0, { (const PTR) 0 } }
 };
+const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U20_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
+    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
+    { 0, { (const PTR) 0 } }
+};
 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [] =
 {
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
@@ -1584,6 +1593,10 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
   { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_SINT, 8, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } }, 
     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
+/* Dsp-40-u20: unsigned 20 bit displacement at offset 40 bits */
+  { "Dsp-40-u20", M32C_OPERAND_DSP_40_U20, HW_H_UINT, 8, 20,
+    { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U20] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
 /* Dsp-40-u24: unsigned 24 bit displacement at offset 40 bits */
   { "Dsp-40-u24", M32C_OPERAND_DSP_40_U24, HW_H_UINT, 8, 24,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } }, 
@@ -1604,6 +1617,10 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
   { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_SINT, 16, 16,
     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } }, 
     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
+/* Dsp-48-u20: unsigned 24 bit displacement at offset 40 bits */
+  { "Dsp-48-u20", M32C_OPERAND_DSP_48_U20, HW_H_UINT, 0, 24,
+    { 2, { (const PTR) &M32C_F_DSP_48_U20_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } }  },
 /* Dsp-48-u24: unsigned 24 bit displacement at offset 48 bits */
   { "Dsp-48-u24", M32C_OPERAND_DSP_48_U24, HW_H_UINT, 0, 24,
     { 2, { (const PTR) &M32C_F_DSP_48_U24_MULTI_IFIELD[0] } }, 
@@ -2025,11 +2042,13 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
 /* src16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
 /* src16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
 /* src16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
+/* src16-16-20-An-relative-QI: m16c dsp:20[An] relative destination QI */
 /* src16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
 /* src16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
 /* src16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
 /* src16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
 /* src16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
+/* src16-16-20-An-relative-HI: m16c dsp:20[An] relative destination HI */
 /* src32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
 /* src32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
 /* src32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
@@ -2134,76 +2153,91 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
 /* dst16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
 /* dst16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
 /* dst16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
+/* dst16-16-20-An-relative-QI: m16c dsp:20[An] relative destination QI */
 /* dst16-24-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
 /* dst16-24-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
 /* dst16-24-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
 /* dst16-24-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
 /* dst16-24-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
+/* dst16-24-20-An-relative-QI: m16c dsp:20[An] relative destination QI */
 /* dst16-32-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
 /* dst16-32-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
 /* dst16-32-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
 /* dst16-32-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
 /* dst16-32-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
+/* dst16-32-20-An-relative-QI: m16c dsp:20[An] relative destination QI */
 /* dst16-40-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
 /* dst16-40-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
 /* dst16-40-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
 /* dst16-40-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
 /* dst16-40-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
+/* dst16-40-20-An-relative-QI: m16c dsp:20[An] relative destination QI */
 /* dst16-48-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
 /* dst16-48-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
 /* dst16-48-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
 /* dst16-48-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
 /* dst16-48-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
+/* dst16-48-20-An-relative-QI: m16c dsp:20[An] relative destination QI */
 /* dst16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
 /* dst16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
 /* dst16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
 /* dst16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
 /* dst16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
+/* dst16-16-20-An-relative-HI: m16c dsp:20[An] relative destination HI */
 /* dst16-24-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
 /* dst16-24-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
 /* dst16-24-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
 /* dst16-24-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
 /* dst16-24-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
+/* dst16-24-20-An-relative-HI: m16c dsp:20[An] relative destination HI */
 /* dst16-32-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
 /* dst16-32-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
 /* dst16-32-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
 /* dst16-32-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
 /* dst16-32-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
+/* dst16-32-20-An-relative-HI: m16c dsp:20[An] relative destination HI */
 /* dst16-40-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
 /* dst16-40-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
 /* dst16-40-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
 /* dst16-40-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
 /* dst16-40-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
+/* dst16-40-20-An-relative-HI: m16c dsp:20[An] relative destination HI */
 /* dst16-48-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
 /* dst16-48-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
 /* dst16-48-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
 /* dst16-48-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
 /* dst16-48-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
+/* dst16-48-20-An-relative-HI: m16c dsp:20[An] relative destination HI */
 /* dst16-16-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
 /* dst16-16-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
 /* dst16-16-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
 /* dst16-16-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
 /* dst16-16-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
+/* dst16-16-20-An-relative-SI: m16c dsp:20[An] relative destination SI */
 /* dst16-24-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
 /* dst16-24-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
 /* dst16-24-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
 /* dst16-24-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
 /* dst16-24-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
+/* dst16-24-20-An-relative-SI: m16c dsp:20[An] relative destination SI */
 /* dst16-32-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
 /* dst16-32-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
 /* dst16-32-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
 /* dst16-32-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
 /* dst16-32-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
+/* dst16-32-20-An-relative-SI: m16c dsp:20[An] relative destination SI */
 /* dst16-40-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
 /* dst16-40-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
 /* dst16-40-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
 /* dst16-40-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
 /* dst16-40-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
+/* dst16-40-20-An-relative-SI: m16c dsp:20[An] relative destination SI */
 /* dst16-48-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
 /* dst16-48-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
 /* dst16-48-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
 /* dst16-48-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
 /* dst16-48-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
+/* dst16-48-20-An-relative-SI: m16c dsp:20[An] relative destination SI */
 /* dst16-16-8-SB-relative-Ext-QI: m16c dsp:8[sb] relative destination QI */
 /* dst16-16-16-SB-relative-Ext-QI: m16c dsp:16[sb] relative destination QI */
 /* dst16-16-8-FB-relative-Ext-QI: m16c dsp:8[fb] relative destination QI */
@@ -2560,12 +2594,18 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
 /* dst16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
 /* dst16-16-8-QI: m16c destination operand of size QI with additional fields at offset 16 */
 /* dst16-16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
+/* dst16-16-16sa-QI: m16c destination operand of size QI with additional fields at offset 16 */
+/* dst16-16-20ar-QI: m16c destination operand of size QI with additional fields at offset 16 */
 /* dst16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
 /* dst16-16-8-HI: m16c destination operand of size HI with additional fields at offset 16 */
 /* dst16-16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
+/* dst16-16-16sa-HI: m16c destination operand of size HI with additional fields at offset 16 */
+/* dst16-16-20ar-HI: m16c destination operand of size HI with additional fields at offset 16 */
 /* dst16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
 /* dst16-16-8-SI: m16c destination operand of size SI with additional fields at offset 16 */
 /* dst16-16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
+/* dst16-16-16sa-SI: m16c destination operand of size SI with additional fields at offset 16 */
+/* dst16-16-20ar-SI: m16c destination operand of size SI with additional fields at offset 16 */
 /* dst16-16-Ext-QI: m16c destination operand of size QI for 'ext' insns with additional fields at offset 16 */
 /* dst16-An-indirect-Mova-HI: m16c addressof An indirect destination HI */
 /* dst16-16-8-An-relative-Mova-HI: m16c addressof dsp:8[An] relative destination HI */
@@ -2589,14 +2629,17 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
 /* dst32-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
 /* dst32-16-8-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
 /* dst32-16-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
+/* dst32-16-16sa-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
 /* dst32-16-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
 /* dst32-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
 /* dst32-16-8-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
 /* dst32-16-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
+/* dst32-16-16sa-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
 /* dst32-16-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
 /* dst32-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
 /* dst32-16-8-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
 /* dst32-16-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
+/* dst32-16-16sa-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
 /* dst32-16-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
 /* dst32-16-ExtUnprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
 /* dst32-16-ExtUnprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
@@ -34487,14 +34530,14 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
     M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, "ldc16.dst-dst16-16-16-absolute-HI", "ldc", 32,
     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } }
   },
-/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* jsri.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
-    M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-An-relative-Unprefixed-SI", "jsri.w", 40,
+    M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-An-relative-Unprefixed-SI", "jsri.a", 40,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-u24} */
+/* jsri.a ${Dsp-16-u24} */
   {
-    M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-absolute-Unprefixed-SI", "jsri.w", 40,
+    M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-absolute-Unprefixed-SI", "jsri.a", 40,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
 /* jsri.a $Dst32RnUnprefixedSI */
@@ -34527,39 +34570,29 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
     M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-indirect-SI", "jsri.a", 16,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
-  {
-    M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "jsri.a", 32,
-    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
-  },
 /* jsri.a ${Dsp-16-u16}[sb] */
   {
-    M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "jsri.a", 32,
+    M32C_INSN_JSRI32A_DST32_16_16SA_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16sa-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "jsri.a", 32,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
 /* jsri.a ${Dsp-16-s16}[fb] */
   {
-    M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "jsri.a", 32,
+    M32C_INSN_JSRI32A_DST32_16_16SA_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16sa-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "jsri.a", 32,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
 /* jsri.a ${Dsp-16-u16} */
   {
-    M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "jsri.a", 32,
+    M32C_INSN_JSRI32A_DST32_16_16SA_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jsri32a-dst32-16-16sa-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "jsri.a", 32,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.a ${Dsp-16-u16}[$Dst16An] */
-  {
-    M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-An-relative-SI", "jsri.a", 32,
-    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
-  },
 /* jsri.a ${Dsp-16-u16}[sb] */
   {
-    M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-SB-relative-SI", "jsri.a", 32,
+    M32C_INSN_JSRI16A_DST16_16_16SA_SI_DST16_16_16_SB_RELATIVE_SI, "jsri16a-dst16-16-16sa-SI-dst16-16-16-SB-relative-SI", "jsri.a", 32,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
 /* jsri.a ${Dsp-16-u16} */
   {
-    M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-absolute-SI", "jsri.a", 32,
+    M32C_INSN_JSRI16A_DST16_16_16SA_SI_DST16_16_16_ABSOLUTE_SI, "jsri16a-dst16-16-16sa-SI-dst16-16-16-absolute-SI", "jsri.a", 32,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
 /* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
@@ -34592,16 +34625,21 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
     M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-FB-relative-SI", "jsri.a", 24,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
+/* jsri.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
-    M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-An-relative-Unprefixed-HI", "jsri.w", 40,
+    M32C_INSN_JSRI32A_DST32_16_24_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-24-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "jsri.a", 40,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-u24} */
+/* jsri.a ${Dsp-16-u24} */
   {
-    M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-absolute-Unprefixed-HI", "jsri.w", 40,
+    M32C_INSN_JSRI32A_DST32_16_24_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jsri32a-dst32-16-24-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "jsri.a", 40,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
+/* jsri.a ${Dsp-16-u20}[$Dst16An] */
+  {
+    M32C_INSN_JSRI16A_DST16_16_20AR_SI_DST16_16_20_AN_RELATIVE_SI, "jsri16a-dst16-16-20ar-SI-dst16-16-20-An-relative-SI", "jsri.a", 40,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
+  },
 /* jsri.w $Dst32RnUnprefixedHI */
   {
     M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "jsri.w", 16,
@@ -34632,69 +34670,74 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
     M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-indirect-HI", "jsri.w", 16,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
-  {
-    M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "jsri.w", 32,
-    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
-  },
-/* jsri.w ${Dsp-16-u16}[sb] */
+/* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
   {
-    M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "jsri.w", 32,
+    M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "jsri.w", 24,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-s16}[fb] */
+/* jsri.w ${Dsp-16-u8}[sb] */
   {
-    M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "jsri.w", 32,
+    M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "jsri.w", 24,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-u16} */
+/* jsri.w ${Dsp-16-s8}[fb] */
   {
-    M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "jsri.w", 32,
+    M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "jsri.w", 24,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-u16}[$Dst16An] */
+/* jsri.w ${Dsp-16-u8}[$Dst16An] */
   {
-    M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-An-relative-HI", "jsri.w", 32,
+    M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-An-relative-HI", "jsri.w", 24,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-u16}[sb] */
+/* jsri.w ${Dsp-16-u8}[sb] */
   {
-    M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-SB-relative-HI", "jsri.w", 32,
+    M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-SB-relative-HI", "jsri.w", 24,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-u16} */
+/* jsri.w ${Dsp-16-s8}[fb] */
   {
-    M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-absolute-HI", "jsri.w", 32,
+    M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-FB-relative-HI", "jsri.w", 24,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
+/* jsri.w ${Dsp-16-u16}[sb] */
   {
-    M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "jsri.w", 24,
+    M32C_INSN_JSRI32W_DST32_16_16SA_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16sa-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "jsri.w", 32,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-u8}[sb] */
+/* jsri.w ${Dsp-16-s16}[fb] */
   {
-    M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "jsri.w", 24,
+    M32C_INSN_JSRI32W_DST32_16_16SA_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16sa-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "jsri.w", 32,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-s8}[fb] */
+/* jsri.w ${Dsp-16-u16} */
   {
-    M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "jsri.w", 24,
+    M32C_INSN_JSRI32W_DST32_16_16SA_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jsri32w-dst32-16-16sa-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "jsri.w", 32,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-u8}[$Dst16An] */
+/* jsri.w ${Dsp-16-u16}[sb] */
   {
-    M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-An-relative-HI", "jsri.w", 24,
+    M32C_INSN_JSRI16W_DST16_16_16SA_HI_DST16_16_16_SB_RELATIVE_HI, "jsri16w-dst16-16-16sa-HI-dst16-16-16-SB-relative-HI", "jsri.w", 32,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-u8}[sb] */
+/* jsri.w ${Dsp-16-u16} */
   {
-    M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-SB-relative-HI", "jsri.w", 24,
+    M32C_INSN_JSRI16W_DST16_16_16SA_HI_DST16_16_16_ABSOLUTE_HI, "jsri16w-dst16-16-16sa-HI-dst16-16-16-absolute-HI", "jsri.w", 32,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
-/* jsri.w ${Dsp-16-s8}[fb] */
+/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
   {
-    M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-FB-relative-HI", "jsri.w", 24,
+    M32C_INSN_JSRI32W_DST32_16_24_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-24-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "jsri.w", 40,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
+  },
+/* jsri.w ${Dsp-16-u24} */
+  {
+    M32C_INSN_JSRI32W_DST32_16_24_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jsri32w-dst32-16-24-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "jsri.w", 40,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } }, { { RL_TYPE_1ADDR, 0 } } } }
+  },
+/* jsri.w ${Dsp-16-u20}[$Dst16An] */
+  {
+    M32C_INSN_JSRI16W_DST16_16_20AR_HI_DST16_16_20_AN_RELATIVE_HI, "jsri16w-dst16-16-20ar-HI-dst16-16-20-An-relative-HI", "jsri.w", 40,
     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_1ADDR, 0 } } } }
   },
 /* jmpi.a $Dst32RnUnprefixedSI */