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| author | Nick Clifton <nickc@redhat.com> | 2000-02-10 21:41:11 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2000-02-10 21:41:11 +0000 |
| commit | 9a10eecf59e4403ac82b17cf637f4ceeb10db6cd (patch) | |
| tree | 77374ae93c7f918e45cbeab0c5d5def02613f2b5 /opcodes/mcore-opc.h | |
| parent | c0326802db31d35783eb6d055b91e65f79b7c94e (diff) | |
| download | binutils-redhat-9a10eecf59e4403ac82b17cf637f4ceeb10db6cd.tar.gz | |
Add support for M340 part.
Diffstat (limited to 'opcodes/mcore-opc.h')
| -rw-r--r-- | opcodes/mcore-opc.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/opcodes/mcore-opc.h b/opcodes/mcore-opc.h index e0bc333b4c..6ff05eeca1 100644 --- a/opcodes/mcore-opc.h +++ b/opcodes/mcore-opc.h @@ -1,5 +1,5 @@ /* Assembler instructions for Motorola's Mcore processor - Copyright (C) 1999 Free Software Foundation, Inc. + Copyright (C) 1999, 2000 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -24,6 +24,7 @@ typedef enum OMa, SI, I7, LS, BR, BL, LR, LJ, RM, RQ, JSR, JMP, OBRa, OBRb, OBRc, OBR2, O1R1, OMb, OMc, SIa, + MULSH, OPSR, JC, JU, JL, RSI, DO21, OB2 } mcore_opclass; @@ -48,6 +49,7 @@ mcore_opcode_info mcore_table[] = { "stop", O0, 0, 0x0004 }, { "wait", O0, 0, 0x0005 }, { "doze", O0, 0, 0x0006 }, + { "idly4", O0, 0, 0x0007 }, { "trap", OT, 0, 0x0008 }, /* SPACE: 0x000C - 0x000F */ /* SPACE: 0x0010 - 0x001F */ @@ -99,6 +101,8 @@ mcore_opcode_info mcore_table[] = { "tst", O2, 0, 0x0E00 }, { "cmpne", O2, 0, 0x0F00 }, { "mfcr", OC, 0, 0x1000 }, + { "psrclr", OPSR, 0, 0x11F0 }, + { "psrset", OPSR, 0, 0x11F8 }, { "mov", O2, 0, 0x1200 }, { "bgenr", O2, 0, 0x1300 }, { "rsub", O2, 0, 0x1400 }, @@ -147,6 +151,8 @@ mcore_opcode_info mcore_table[] = { "movi", I7, 0, 0x6000 }, #define MCORE_INST_BMASKI_ALT 0x6000 #define MCORE_INST_BGENI_ALT 0x6000 + { "mulsh", MULSH, 0, 0x6800 }, + { "muls.h", MULSH, 0, 0x6800 }, /* SPACE: 0x6900 - 0x6FFF */ { "jmpi", LJ, 1, 0x7000 }, { "jsri", LJ, 0, 0x7F00 }, |