[cgen]

	* intrinsics.scm: Updates to support IVC2.
	(belongs-to-group?): Check IVC2 slots.
	(-slots-attribute): New.
	(targets::attributes): Add SLOTS.
	(target:add-well-known-intrinsics): Add CPMOV.
	(md-insn): Add CPTYPE and CRET?.
	(add-md-insn): Likewise.
	(add-intrinsic-for-isa): Disable the duplicate tests, as IVC2 has
	duplicate insns with different bit patterns.
	(write-cgen-insn?): Add cret? support.
	(intrinsics.h): Add vector types.
	(runtime-op): Add vector support.
	(intrinsic-protos.h): Let GCC define its types.  Add cret? support.

	* cpu/mep-core.cpu: Add CPTYPE and CRET attributes.
	* cpu/mep-ivc2.cpu: Update all insns to include type information.
	(h-cr-ivc2): Default to typeless.
	(h-ccr-ivc2): Fix register width.
	(SLOTS): Fix values and default.
	(ivc2_*): Add control register names.
	(crop, crqp, crpp, croc, crqc, crpc): Default to typeless.

[opcodes]

	* mep-desc.c: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-dis.c: Regenerate.
	* mep-ibld.c: Regenerate.
	* mep-opc.c: Regenerate.

[sid/component/cgen-cpu/mep]

	* ivc2-cop.cxx (ivc2_cphadd_w): Change to return value.
	(ivc2_cpsubaca0u_b): Remove debug line.
	* ivc2-cpu.h (ivc2_cpccadd_b): Change to return value.
	* mep-cop1-16-decode.cxx: Regenerate.
	* mep-cop1-16-sem.cxx: Regenerate.
	* mep-cop1-32-decode.cxx: Regenerate.
	* mep-cop1-32-sem.cxx: Regenerate.
	* mep-cop1-48-decode.cxx: Regenerate.
	* mep-cop1-48-sem.cxx: Regenerate.
	* mep-cop1-64-decode.cxx: Regenerate.
	* mep-cop1-64-sem.cxx: Regenerate.
	* mep-core1-decode.cxx: Regenerate.
	* mep-cpu.h: Regenerate.
	* mep-decode.cxx: Regenerate.
	* mep-desc.h: Regenerate.

1 files changed, 322 insertions, 0 deletions

diff --git a/opcodes/mep-ibld.c b/opcodes/mep-ibld.c
index 05767bec7e..e8e971e5e2 100644
--- a/opcodes/mep-ibld.c
+++ b/opcodes/mep-ibld.c
@@ -878,6 +878,52 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_IVC_X_6_3 :
       errmsg = insert_normal (cd, fields->f_ivc2_3u6, 0, 0, 6, 3, 32, total_length, buffer);
       break;
+    case MEP_OPERAND_IVC2_ACC0_0 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_1 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_2 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_3 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_4 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_5 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_6 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_7 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_0 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_1 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_2 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_3 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_4 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_5 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_6 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_7 :
+      break;
+    case MEP_OPERAND_IVC2_CC :
+      break;
+    case MEP_OPERAND_IVC2_COFA0 :
+      break;
+    case MEP_OPERAND_IVC2_COFA1 :
+      break;
+    case MEP_OPERAND_IVC2_COFR0 :
+      break;
+    case MEP_OPERAND_IVC2_COFR1 :
+      break;
+    case MEP_OPERAND_IVC2_CSAR0 :
+      break;
+    case MEP_OPERAND_IVC2_CSAR1 :
+      break;
     case MEP_OPERAND_IVC2C3CCRN :
       {
 {
@@ -1459,6 +1505,52 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
     case MEP_OPERAND_IVC_X_6_3 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 3, 32, total_length, pc, & fields->f_ivc2_3u6);
       break;
+    case MEP_OPERAND_IVC2_ACC0_0 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_1 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_2 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_3 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_4 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_5 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_6 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_7 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_0 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_1 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_2 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_3 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_4 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_5 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_6 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_7 :
+      break;
+    case MEP_OPERAND_IVC2_CC :
+      break;
+    case MEP_OPERAND_IVC2_COFA0 :
+      break;
+    case MEP_OPERAND_IVC2_COFA1 :
+      break;
+    case MEP_OPERAND_IVC2_COFR0 :
+      break;
+    case MEP_OPERAND_IVC2_COFR1 :
+      break;
+    case MEP_OPERAND_IVC2_CSAR0 :
+      break;
+    case MEP_OPERAND_IVC2_CSAR1 :
+      break;
     case MEP_OPERAND_IVC2C3CCRN :
       {
         length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 2, 32, total_length, pc, & fields->f_ivc2_ccrn_c3hi);
@@ -1917,6 +2009,75 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_IVC_X_6_3 :
       value = fields->f_ivc2_3u6;
       break;
+    case MEP_OPERAND_IVC2_ACC0_0 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_1 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_2 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_3 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_4 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_5 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_6 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_7 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_0 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_1 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_2 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_3 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_4 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_5 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_6 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_7 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_CC :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_COFA0 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_COFA1 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_COFR0 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_COFR1 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_CSAR0 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_CSAR1 :
+      value = 0;
+      break;
     case MEP_OPERAND_IVC2C3CCRN :
       value = fields->f_ivc2_ccrn_c3;
       break;
@@ -2300,6 +2461,75 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_IVC_X_6_3 :
       value = fields->f_ivc2_3u6;
       break;
+    case MEP_OPERAND_IVC2_ACC0_0 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_1 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_2 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_3 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_4 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_5 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_6 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC0_7 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_0 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_1 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_2 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_3 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_4 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_5 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_6 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_ACC1_7 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_CC :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_COFA0 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_COFA1 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_COFR0 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_COFR1 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_CSAR0 :
+      value = 0;
+      break;
+    case MEP_OPERAND_IVC2_CSAR1 :
+      value = 0;
+      break;
     case MEP_OPERAND_IVC2C3CCRN :
       value = fields->f_ivc2_ccrn_c3;
       break;
@@ -2684,6 +2914,52 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_IVC_X_6_3 :
       fields->f_ivc2_3u6 = value;
       break;
+    case MEP_OPERAND_IVC2_ACC0_0 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_1 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_2 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_3 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_4 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_5 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_6 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_7 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_0 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_1 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_2 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_3 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_4 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_5 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_6 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_7 :
+      break;
+    case MEP_OPERAND_IVC2_CC :
+      break;
+    case MEP_OPERAND_IVC2_COFA0 :
+      break;
+    case MEP_OPERAND_IVC2_COFA1 :
+      break;
+    case MEP_OPERAND_IVC2_COFR0 :
+      break;
+    case MEP_OPERAND_IVC2_COFR1 :
+      break;
+    case MEP_OPERAND_IVC2_CSAR0 :
+      break;
+    case MEP_OPERAND_IVC2_CSAR1 :
+      break;
     case MEP_OPERAND_IVC2C3CCRN :
       fields->f_ivc2_ccrn_c3 = value;
       break;
@@ -3041,6 +3317,52 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
     case MEP_OPERAND_IVC_X_6_3 :
       fields->f_ivc2_3u6 = value;
       break;
+    case MEP_OPERAND_IVC2_ACC0_0 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_1 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_2 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_3 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_4 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_5 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_6 :
+      break;
+    case MEP_OPERAND_IVC2_ACC0_7 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_0 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_1 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_2 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_3 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_4 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_5 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_6 :
+      break;
+    case MEP_OPERAND_IVC2_ACC1_7 :
+      break;
+    case MEP_OPERAND_IVC2_CC :
+      break;
+    case MEP_OPERAND_IVC2_COFA0 :
+      break;
+    case MEP_OPERAND_IVC2_COFA1 :
+      break;
+    case MEP_OPERAND_IVC2_COFR0 :
+      break;
+    case MEP_OPERAND_IVC2_COFR1 :
+      break;
+    case MEP_OPERAND_IVC2_CSAR0 :
+      break;
+    case MEP_OPERAND_IVC2_CSAR1 :
+      break;
     case MEP_OPERAND_IVC2C3CCRN :
       fields->f_ivc2_ccrn_c3 = value;
       break;