Update function declarations to ISO C90 formatting

1 files changed, 63 insertions, 139 deletions

diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index d69157d310..c6dfe8ba47 100644
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -1,5 +1,5 @@
 /* Assemble V850 instructions.
-   Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003
+   Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
@@ -14,7 +14,8 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include "sysdep.h"
 #include "opcode/v850.h"
@@ -34,30 +35,6 @@
 
 /* Two-word opcodes.  */
 #define two(x,y)	((unsigned int) (x) | ((unsigned int) (y) << 16))
-
-static long unsigned insert_d9      PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d9     PARAMS ((long unsigned, int *));
-static long unsigned insert_d22     PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d22    PARAMS ((long unsigned, int *));
-static long unsigned insert_d16_15  PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d16_15 PARAMS ((long unsigned, int *));
-static long unsigned insert_d8_7    PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d8_7   PARAMS ((long unsigned, int *));
-static long unsigned insert_d8_6    PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d8_6   PARAMS ((long unsigned, int *));
-static long unsigned insert_d5_4    PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d5_4   PARAMS ((long unsigned, int *));
-static long unsigned insert_d16_16  PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_d16_16 PARAMS ((long unsigned, int *));
-static long unsigned insert_i9      PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_i9     PARAMS ((long unsigned, int *));
-static long unsigned insert_u9      PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_u9     PARAMS ((long unsigned, int *));
-static long unsigned insert_spe     PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_spe    PARAMS ((long unsigned, int *));
-static long unsigned insert_i5div   PARAMS ((long unsigned, long, const char **));
-static long unsigned extract_i5div  PARAMS ((long unsigned, int *));
-
 
 /* The functions used to insert and extract complicated operands.  */
 
@@ -73,10 +50,7 @@ static const char * not_aligned  = N_ ("displacement value is not aligned");
 static const char * immediate_out_of_range = N_ ("immediate value is out of range");
 
 static unsigned long
-insert_d9 (insn, value, errmsg)
-     unsigned long insn;
-     long          value;
-     const char ** errmsg;
+insert_d9 (unsigned long insn, long value, const char ** errmsg)
 {
   if (value > 0xff || value < -0x100)
     {
@@ -88,13 +62,11 @@ insert_d9 (insn, value, errmsg)
   else if ((value % 2) != 0)
     * errmsg = _("branch to odd offset");
 
-  return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
+  return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3);
 }
 
 static unsigned long
-extract_d9 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
 
@@ -105,10 +77,7 @@ extract_d9 (insn, invalid)
 }
 
 static unsigned long
-insert_d22 (insn, value, errmsg)
-     unsigned long insn;
-     long          value;
-     const char ** errmsg;
+insert_d22 (unsigned long insn, long value, const char ** errmsg)
 {
   if (value > 0x1fffff || value < -0x200000)
     {
@@ -120,13 +89,11 @@ insert_d22 (insn, value, errmsg)
   else if ((value % 2) != 0)
     * errmsg = _("branch to odd offset");
 
-  return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16));
+  return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16);
 }
 
 static unsigned long
-extract_d22 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d22 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16);
 
@@ -134,10 +101,7 @@ extract_d22 (insn, invalid)
 }
 
 static unsigned long
-insert_d16_15 (insn, value, errmsg)
-     unsigned long insn;
-     long          value;
-     const char ** errmsg;
+insert_d16_15 (unsigned long insn, long value, const char ** errmsg)
 {
   if (value > 0x7fff || value < -0x8000)
     {
@@ -153,9 +117,7 @@ insert_d16_15 (insn, value, errmsg)
 }
 
 static unsigned long
-extract_d16_15 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d16_15 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   signed long ret = (insn & 0xfffe0000);
 
@@ -163,10 +125,7 @@ extract_d16_15 (insn, invalid)
 }
 
 static unsigned long
-insert_d8_7 (insn, value, errmsg)
-     unsigned long insn;
-     long          value;
-     const char ** errmsg;
+insert_d8_7 (unsigned long insn, long value, const char ** errmsg)
 {
   if (value > 0xff || value < 0)
     {
@@ -180,13 +139,11 @@ insert_d8_7 (insn, value, errmsg)
 
   value >>= 1;
 
-  return (insn | (value & 0x7f));
+  return insn | (value & 0x7f);
 }
 
 static unsigned long
-extract_d8_7 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d8_7 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   unsigned long ret = (insn & 0x7f);
 
@@ -194,10 +151,7 @@ extract_d8_7 (insn, invalid)
 }
 
 static unsigned long
-insert_d8_6 (insn, value, errmsg)
-     unsigned long insn;
-     long          value;
-     const char ** errmsg;
+insert_d8_6 (unsigned long insn, long value, const char ** errmsg)
 {
   if (value > 0xff || value < 0)
     {
@@ -211,13 +165,11 @@ insert_d8_6 (insn, value, errmsg)
 
   value >>= 1;
 
-  return (insn | (value & 0x7e));
+  return insn | (value & 0x7e);
 }
 
 static unsigned long
-extract_d8_6 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d8_6 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   unsigned long ret = (insn & 0x7e);
 
@@ -225,10 +177,7 @@ extract_d8_6 (insn, invalid)
 }
 
 static unsigned long
-insert_d5_4 (insn, value, errmsg)
-     unsigned long insn;
-     long          value;
-     const char ** errmsg;
+insert_d5_4 (unsigned long insn, long value, const char ** errmsg)
 {
   if (value > 0x1f || value < 0)
     {
@@ -242,13 +191,11 @@ insert_d5_4 (insn, value, errmsg)
 
   value >>= 1;
 
-  return (insn | (value & 0x0f));
+  return insn | (value & 0x0f);
 }
 
 static unsigned long
-extract_d5_4 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d5_4 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   unsigned long ret = (insn & 0x0f);
 
@@ -256,36 +203,28 @@ extract_d5_4 (insn, invalid)
 }
 
 static unsigned long
-insert_d16_16 (insn, value, errmsg)
-     unsigned long insn;
-     signed long   value;
-     const char ** errmsg;
+insert_d16_16 (unsigned long insn, signed long value, const char ** errmsg)
 {
   if (value > 0x7fff || value < -0x8000)
     * errmsg = _(out_of_range);
 
-  return (insn | ((value & 0xfffe) << 16) | ((value & 1) << 5));
+  return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5);
 }
 
 static unsigned long
-extract_d16_16 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_d16_16 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   signed long ret = insn & 0xfffe0000;
 
   ret >>= 16;
 
   ret |= ((insn & 0x20) >> 5);
-  
+
   return ret;
 }
 
 static unsigned long
-insert_i9 (insn, value, errmsg)
-     unsigned long insn;
-     signed long   value;
-     const char ** errmsg;
+insert_i9 (unsigned long insn, signed long value, const char ** errmsg)
 {
   if (value > 0xff || value < -0x100)
     * errmsg = _(immediate_out_of_range);
@@ -294,9 +233,7 @@ insert_i9 (insn, value, errmsg)
 }
 
 static unsigned long
-extract_i9 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_i9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   signed long ret = insn & 0x003c0000;
 
@@ -304,17 +241,15 @@ extract_i9 (insn, invalid)
   ret >>= 23;
 
   ret |= (insn & 0x1f);
-  
+
   return ret;
 }
 
 static unsigned long
-insert_u9 (insn, v, errmsg)
-     unsigned long insn;
-     long v;
-     const char ** errmsg;
+insert_u9 (unsigned long insn, long v, const char ** errmsg)
 {
   unsigned long value = (unsigned long) v;
+
   if (value > 0x1ff)
     * errmsg = _(immediate_out_of_range);
 
@@ -322,24 +257,19 @@ insert_u9 (insn, v, errmsg)
 }
 
 static unsigned long
-extract_u9 (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_u9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   unsigned long ret = insn & 0x003c0000;
 
   ret >>= 13;
 
   ret |= (insn & 0x1f);
-  
+
   return ret;
 }
 
 static unsigned long
-insert_spe (insn, v, errmsg)
-     unsigned long insn;
-     long v;
-     const char ** errmsg;
+insert_spe (unsigned long insn, long v, const char ** errmsg)
 {
   unsigned long value = (unsigned long) v;
 
@@ -350,18 +280,14 @@ insert_spe (insn, v, errmsg)
 }
 
 static unsigned long
-extract_spe (insn, invalid)
-     unsigned long insn ATTRIBUTE_UNUSED;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_spe (unsigned long insn ATTRIBUTE_UNUSED,
+	     int * invalid ATTRIBUTE_UNUSED)
 {
   return 3;
 }
 
 static unsigned long
-insert_i5div (insn, v, errmsg)
-     unsigned long insn;
-     long v;
-     const char ** errmsg;
+insert_i5div (unsigned long insn, long v, const char ** errmsg)
 {
   unsigned long value = (unsigned long) v;
 
@@ -376,21 +302,19 @@ insert_i5div (insn, v, errmsg)
     * errmsg = _("immediate value must be even");
 
   value = 32 - value;
-  
+
   return insn | ((value & 0x1e) << 17);
 }
 
 static unsigned long
-extract_i5div (insn, invalid)
-     unsigned long insn;
-     int *         invalid ATTRIBUTE_UNUSED;
+extract_i5div (unsigned long insn, int * invalid ATTRIBUTE_UNUSED)
 {
   unsigned long ret = insn & 0x3c0000;
 
   ret >>= 17;
 
   ret = 32 - ret;
-  
+
   return ret;
 }
 
@@ -401,11 +325,11 @@ extract_i5div (insn, invalid)
 const struct v850_operand v850_operands[] =
 {
 #define UNUSED	0
-  { 0, 0, NULL, NULL, 0 }, 
+  { 0, 0, NULL, NULL, 0 },
 
 /* The R1 field in a format 1, 6, 7, or 9 insn.  */
 #define R1	(UNUSED + 1)
-  { 5, 0, NULL, NULL, V850_OPERAND_REG }, 
+  { 5, 0, NULL, NULL, V850_OPERAND_REG },
 
 /* As above, but register 0 is not allowed.  */
 #define R1_NOTR0 (R1 + 1)
@@ -421,7 +345,7 @@ const struct v850_operand v850_operands[] =
 
 /* The imm5 field in a format 2 insn.  */
 #define I5	(R2_NOTR0 + 1)
-  { 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, 
+  { 5, 0, NULL, NULL, V850_OPERAND_SIGNED },
 
 /* The unsigned imm5 field in a format 2 insn.  */
 #define I5U	(I5 + 1)
@@ -429,7 +353,7 @@ const struct v850_operand v850_operands[] =
 
 /* The imm16 field in a format 6 insn.  */
 #define I16	(I5U + 1)
-  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, 
+  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED },
 
 /* The signed disp7 field in a format 4 insn.  */
 #define D7	(I16 + 1)
@@ -437,7 +361,7 @@ const struct v850_operand v850_operands[] =
 
 /* The disp16 field in a format 6 insn.  */
 #define D16_15	(D7 + 1)
-  { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, 
+  { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED },
 
 /* The 3 bit immediate field in format 8 insn.  */
 #define B3	(D16_15 + 1)
@@ -465,7 +389,7 @@ const struct v850_operand v850_operands[] =
 
 /* The imm16 field (unsigned) in a format 6 insn.  */
 #define I16U	(EP + 1)
-  { 16, 16, NULL, NULL, 0}, 
+  { 16, 16, NULL, NULL, 0},
 
 /* The R2 field as a system register.  */
 #define SR2	(I16U + 1)
@@ -473,7 +397,7 @@ const struct v850_operand v850_operands[] =
 
 /* The disp16 field in a format 8 insn.  */
 #define D16	(SR2 + 1)
-  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, 
+  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED },
 
 /* The DISP9 field in a format 3 insn, relaxable.  */
 #define D9_RELAX	(D16 + 1)
@@ -495,7 +419,7 @@ const struct v850_operand v850_operands[] =
 
 /* The disp16 field in an format 7 unsigned byte load insn.  */
 #define D16_16	(D5_4 + 1)
-  { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, 
+  { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 },
 
 /* Third register in conditional moves.  */
 #define R3	(D16_16 + 1)
@@ -507,31 +431,31 @@ const struct v850_operand v850_operands[] =
 
 /* The imm9 field in a multiply word.  */
 #define I9	(MOVCC + 1)
-  { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, 
+  { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED },
 
 /* The unsigned imm9 field in a multiply word.  */
 #define U9	(I9 + 1)
-  { 9, 0, insert_u9, extract_u9, 0 }, 
+  { 9, 0, insert_u9, extract_u9, 0 },
 
 /* A list of registers in a prepare/dispose instruction.  */
 #define LIST12	(U9 + 1)
-  { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, 
+  { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP },
 
 /* The IMM6 field in a call instruction.  */
 #define I6	(LIST12 + 1)
-  { 6, 0, NULL, NULL, 0 }, 
+  { 6, 0, NULL, NULL, 0 },
 
 /* The 16 bit immediate following a 32 bit instruction.  */
 #define IMM16	(I6 + 1)
-  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 }, 
+  { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 },
 
 /* The 32 bit immediate following a 32 bit instruction.  */
 #define IMM32	(IMM16 + 1)
-  { 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, 
+  { 0, 0, NULL, NULL, V850E_IMMEDIATE32 },
 
 /* The imm5 field in a push/pop instruction.  */
 #define IMM5	(IMM32 + 1)
-  { 5, 1, NULL, NULL, 0 }, 
+  { 5, 1, NULL, NULL, 0 },
 
 /* Reg2 in dispose instruction.  */
 #define R2DISPOSE	(IMM5 + 1)
@@ -543,17 +467,17 @@ const struct v850_operand v850_operands[] =
 
 /* The IMM5 field in a divide N step instruction.  */
 #define I5DIV	(SP + 1)
-  { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, 
+  { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED },
 
   /* The list of registers in a PUSHMH/POPMH instruction.  */
 #define LIST18_H (I5DIV + 1)
-  { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP }, 
+  { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP },
 
   /* The list of registers in a PUSHML/POPML instruction.  */
 #define LIST18_L (LIST18_H + 1)
   /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c.  */
   { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP },
-} ; 
+};
 
 
 /* Reg - Reg instruction format (Format I).  */
@@ -586,7 +510,7 @@ const struct v850_operand v850_operands[] =
    OPERANDS is the list of operands.
    MEMOP specifies which operand (if any) is a memory operand.
    PROCESSORS specifies which CPU(s) support the opcode.
-   
+
    The disassembler reads the table in order and prints the first
    instruction which matches, so this table is sorted to put more
    specific instructions before more general instructions.  It is also
@@ -609,7 +533,7 @@ const struct v850_opcode v850_opcodes[] =
 { "dbtrap",	one (0xf840),		one (0xffff),		{UNUSED},   		0, PROCESSOR_V850E1 },
 
 { "jmp",	one (0x0060),		one (0xffe0),	      	{R1}, 			1, PROCESSOR_ALL },
-  
+
 /* Load/store instructions.  */
 { "sld.bu",     one (0x0060),		one (0x07f0),         	{D4,   EP,   R2_NOTR0},	1, PROCESSOR_V850E1 },
 { "sld.bu",     one (0x0060),		one (0x07f0),         	{D4,   EP,   R2_NOTR0},	1, PROCESSOR_V850E },
@@ -641,7 +565,7 @@ const struct v850_opcode v850_opcodes[] =
 { "ld.h",	two (0x0720, 0x0000),	two (0x07e0, 0x0001), 	{D16_15, R1, R2}, 	1, PROCESSOR_ALL },
 { "ld.w",	two (0x0720, 0x0001),	two (0x07e0, 0x0001), 	{D16_15, R1, R2}, 	1, PROCESSOR_ALL },
 { "ld.bu",	two (0x0780, 0x0001),   two (0x07c0, 0x0001), 	{D16_16, R1, R2_NOTR0},	1, PROCESSOR_NOT_V850 },
-{ "ld.hu",	two (0x07e0, 0x0001),   two (0x07e0, 0x0001), 	{D16_15, R1, R2_NOTR0},	1, PROCESSOR_NOT_V850 },  
+{ "ld.hu",	two (0x07e0, 0x0001),   two (0x07e0, 0x0001), 	{D16_15, R1, R2_NOTR0},	1, PROCESSOR_NOT_V850 },
 { "st.b",	two (0x0740, 0x0000),	two (0x07e0, 0x0000), 	{R2, D16, R1}, 		2, PROCESSOR_ALL },
 { "st.h",	two (0x0760, 0x0000),	two (0x07e0, 0x0001), 	{R2, D16_15, R1}, 	2, PROCESSOR_ALL },
 { "st.w",	two (0x0760, 0x0001),	two (0x07e0, 0x0001), 	{R2, D16_15, R1}, 	2, PROCESSOR_ALL },
@@ -675,7 +599,7 @@ const struct v850_opcode v850_opcodes[] =
 { "divhu",	two (0x07e0, 0x0282),   two (0x07e0, 0x07ff), 	{R1, R2, R3}, 		0, PROCESSOR_NOT_V850 },
 { "divh",	two (0x07e0, 0x0280),   two (0x07e0, 0x07ff), 	{R1, R2, R3}, 		0, PROCESSOR_NOT_V850 },
 { "divh",	OP  (0x02),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
-  
+
 { "nop",	one (0x00),		one (0xffff),		{0}, 			0, PROCESSOR_ALL },
 { "mov",	OP  (0x10),		OP_MASK,		{I5, R2_NOTR0},		0, PROCESSOR_ALL },
 { "mov",	one (0x0620),		one (0xffe0),		{IMM32, R1_NOTR0},	0, PROCESSOR_NOT_V850 },
@@ -692,7 +616,7 @@ const struct v850_opcode v850_opcodes[] =
 { "mulhi",	OP  (0x37),		OP_MASK,		{I16, R1, R2_NOTR0},	0, PROCESSOR_ALL },
 { "cmp",	OP  (0x0f),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
 { "cmp",	OP  (0x13),		OP_MASK,		IF2, 			0, PROCESSOR_ALL },
-  
+
 /* Saturated operation instructions.  */
 { "satadd",	OP (0x11),		OP_MASK,		{I5, R2_NOTR0},		0, PROCESSOR_ALL },
 { "satadd",	OP (0x06),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
@@ -772,9 +696,9 @@ const struct v850_opcode v850_opcodes[] =
 { "jnz",	BOP (0xa),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "jsa",	BOP (0xd),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
 { "jbr",	BOP (0x5),		BOP_MASK,		IF3, 			0, PROCESSOR_ALL },
-  
+
 { "jr",		one (0x0780),		two (0xffc0, 0x0001),	{D22}, 			0, PROCESSOR_ALL },
-{ "jarl",	one (0x0780),		two (0x07c0, 0x0001),	{D22, R2}, 		0, PROCESSOR_ALL}, 
+{ "jarl",	one (0x0780),		two (0x07c0, 0x0001),	{D22, R2}, 		0, PROCESSOR_ALL },
 
 /* Bit manipulation instructions.  */
 { "set1",	two (0x07c0, 0x0000),	two (0xc7e0, 0x0000),	{B3, D16, R1}, 		2, PROCESSOR_ALL },