Add support for the M32R2 processor.

9 files changed, 528 insertions, 175 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 522f611061..bc76e638c3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2003-12-03  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* m32r-asm.c: Regenerate.
+	* m32r-desc.c: Regenerate.
+	* m32r-desc.h: Regenerate.
+	* m32r-dis.c: Regenerate.
+	* m32r-ibld.c: Regenerate.
+	* m32r-opc.c: Regenerate.
+	* m32r-opc.h: Regenerate.
+	* m32r-opinst.c: Regenerate.
+
 2003-12-02  Kazu Hirata  <kazu@cs.umass.edu>
 
 	* alpha-opc.c: Remove ARGSUSED.
diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c
index a8c9485f20..8c2cc81ea8 100644
--- a/opcodes/m32r-asm.c
+++ b/opcodes/m32r-asm.c
@@ -147,7 +147,11 @@ parse_slo16 (cd, strp, opindex, valuep)
       ++*strp;
       if (errmsg == NULL
 	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
-	value &= 0xffff;
+        {
+	  value &= 0xffff;
+          if (value & 0x8000)
+             value |= 0xffff0000;
+        }
       *valuep = value;
       return errmsg;
     }
@@ -310,12 +314,18 @@ m32r_cgen_parse_operand (cd, opindex, strp, fields)
         fields->f_uimm24 = value;
       }
       break;
+    case M32R_OPERAND_UIMM3 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM3, &fields->f_uimm3);
+      break;
     case M32R_OPERAND_UIMM4 :
       errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM4, &fields->f_uimm4);
       break;
     case M32R_OPERAND_UIMM5 :
       errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM5, &fields->f_uimm5);
       break;
+    case M32R_OPERAND_UIMM8 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM8, &fields->f_uimm8);
+      break;
     case M32R_OPERAND_ULO16 :
       errmsg = parse_ulo16 (cd, strp, M32R_OPERAND_ULO16, &fields->f_uimm16);
       break;
diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index 023ab62bb9..711aff03bb 100644
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -48,6 +48,7 @@ static const CGEN_ATTR_ENTRY MACH_attr[] =
   { "base", MACH_BASE },
   { "m32r", MACH_M32R },
   { "m32rx", MACH_M32RX },
+  { "m32r2", MACH_M32R2 },
   { "max", MACH_MAX },
   { 0, 0 }
 };
@@ -65,6 +66,7 @@ static const CGEN_ATTR_ENTRY PIPE_attr[] =
   { "O", PIPE_O },
   { "S", PIPE_S },
   { "OS", PIPE_OS },
+  { "O_OS", PIPE_O_OS },
   { 0, 0 }
 };
 
@@ -123,6 +125,8 @@ const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
   { "SPECIAL", &bool_attr[0], &bool_attr[0] },
+  { "SPECIAL_M32R", &bool_attr[0], &bool_attr[0] },
+  { "SPECIAL_FLOAT", &bool_attr[0], &bool_attr[0] },
   { 0, 0, 0 }
 };
 
@@ -138,6 +142,7 @@ static const CGEN_ISA m32r_cgen_isa_table[] = {
 static const CGEN_MACH m32r_cgen_mach_table[] = {
   { "m32r", "m32r", MACH_M32R, 0 },
   { "m32rx", "m32rx", MACH_M32RX, 0 },
+  { "m32r2", "m32r2", MACH_M32R2, 0 },
   { 0, 0, 0, 0 }
 };
 
@@ -180,6 +185,7 @@ static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
   { "bpc", 6, {0, {0}}, 0, 0 },
   { "bbpsw", 8, {0, {0}}, 0, 0 },
   { "bbpc", 14, {0, {0}}, 0, 0 },
+  { "evb", 5, {0, {0}}, 0, 0 },
   { "cr0", 0, {0, {0}}, 0, 0 },
   { "cr1", 1, {0, {0}}, 0, 0 },
   { "cr2", 2, {0, {0}}, 0, 0 },
@@ -201,7 +207,7 @@ static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
 CGEN_KEYWORD m32r_cgen_opval_cr_names =
 {
   & m32r_cgen_opval_cr_names_entries[0],
-  23,
+  24,
   0, 0, 0, 0, ""
 };
 
@@ -241,7 +247,7 @@ const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
   { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
+  { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
   { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
   { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
@@ -273,8 +279,10 @@ const CGEN_IFLD m32r_cgen_ifld_table[] =
   { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
   { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
@@ -287,6 +295,7 @@ const CGEN_IFLD m32r_cgen_ifld_table[] =
   { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
   { 0, 0, 0, 0, 0, 0, {0, {0}} }
@@ -354,6 +363,10 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
   { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, 
     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* uimm3: 3 bit unsigned number */
+  { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
+    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 /* uimm4: 4 bit trap number */
   { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } }, 
@@ -362,6 +375,10 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
   { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } }, 
     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* uimm8: 8 bit unsigned immediate */
+  { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
+    { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 /* uimm16: 16 bit unsigned immediate */
   { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, 
@@ -369,19 +386,19 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
 /* imm1: 1 bit immediate */
   { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } }, 
-    { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } }  },
+    { 0|A(HASH_PREFIX), { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
 /* accd: accumulator destination register */
   { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } }, 
-    { 0, { (1<<MACH_M32RX) } }  },
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
 /* accs: accumulator source register */
   { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } }, 
-    { 0, { (1<<MACH_M32RX) } }  },
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
 /* acc: accumulator reg (d) */
   { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } }, 
-    { 0, { (1<<MACH_M32RX) } }  },
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
 /* hash: # prefix */
   { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
     { 0, { (const PTR) 0 } }, 
@@ -564,12 +581,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* bcl.s $disp8 */
   {
     M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
-    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* bcl.l $disp24 */
   {
     M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
-    { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* bnc.s $disp8 */
   {
@@ -599,12 +616,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* bncl.s $disp8 */
   {
     M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
-    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* bncl.l $disp24 */
   {
     M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
-    { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* cmp $src1,$src2 */
   {
@@ -629,12 +646,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* cmpeq $src1,$src2 */
   {
     M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_OS } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
   },
 /* cmpz $src2 */
   {
     M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_OS } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
   },
 /* div $dr,$sr */
   {
@@ -656,20 +673,55 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
     M32R_INSN_REMU, "remu", "remu", 32,
     { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
+/* remh $dr,$sr */
+  {
+    M32R_INSN_REMH, "remh", "remh", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
+/* remuh $dr,$sr */
+  {
+    M32R_INSN_REMUH, "remuh", "remuh", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
+/* remb $dr,$sr */
+  {
+    M32R_INSN_REMB, "remb", "remb", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
+/* remub $dr,$sr */
+  {
+    M32R_INSN_REMUB, "remub", "remub", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
+/* divuh $dr,$sr */
+  {
+    M32R_INSN_DIVUH, "divuh", "divuh", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
+/* divb $dr,$sr */
+  {
+    M32R_INSN_DIVB, "divb", "divb", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
+/* divub $dr,$sr */
+  {
+    M32R_INSN_DIVUB, "divub", "divub", 32,
+    { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+  },
 /* divh $dr,$sr */
   {
     M32R_INSN_DIVH, "divh", "divh", 32,
-    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* jc $sr */
   {
     M32R_INSN_JC, "jc", "jc", 16,
-    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* jnc $sr */
   {
     M32R_INSN_JNC, "jnc", "jnc", 16,
-    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* jl $sr */
   {
@@ -764,7 +816,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* machi $src1,$src2,$acc */
   {
     M32R_INSN_MACHI_A, "machi-a", "machi", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* maclo $src1,$src2 */
   {
@@ -774,7 +826,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* maclo $src1,$src2,$acc */
   {
     M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* macwhi $src1,$src2 */
   {
@@ -784,7 +836,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* macwhi $src1,$src2,$acc */
   {
     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* macwlo $src1,$src2 */
   {
@@ -794,7 +846,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* macwlo $src1,$src2,$acc */
   {
     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mul $dr,$sr */
   {
@@ -809,7 +861,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mulhi $src1,$src2,$acc */
   {
     M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mullo $src1,$src2 */
   {
@@ -819,7 +871,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mullo $src1,$src2,$acc */
   {
     M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mulwhi $src1,$src2 */
   {
@@ -829,7 +881,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mulwhi $src1,$src2,$acc */
   {
     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mulwlo $src1,$src2 */
   {
@@ -839,7 +891,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mulwlo $src1,$src2,$acc */
   {
     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mv $dr,$sr */
   {
@@ -854,7 +906,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mvfachi $dr,$accs */
   {
     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mvfaclo $dr */
   {
@@ -864,7 +916,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mvfaclo $dr,$accs */
   {
     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mvfacmi $dr */
   {
@@ -874,7 +926,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mvfacmi $dr,$accs */
   {
     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mvfc $dr,$scr */
   {
@@ -889,7 +941,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mvtachi $src1,$accs */
   {
     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mvtaclo $src1 */
   {
@@ -899,7 +951,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* mvtaclo $src1,$accs */
   {
     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mvtc $sr,$dcr */
   {
@@ -929,7 +981,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* rac $accd,$accs,$imm1 */
   {
     M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* rach */
   {
@@ -939,7 +991,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* rach $accd,$accs,$imm1 */
   {
     M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* rte */
   {
@@ -954,7 +1006,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* sll $dr,$sr */
   {
     M32R_INSN_SLL, "sll", "sll", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
   },
 /* sll3 $dr,$sr,$simm16 */
   {
@@ -964,12 +1016,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* slli $dr,$uimm5 */
   {
     M32R_INSN_SLLI, "slli", "slli", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
   },
 /* sra $dr,$sr */
   {
     M32R_INSN_SRA, "sra", "sra", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
   },
 /* sra3 $dr,$sr,$simm16 */
   {
@@ -979,12 +1031,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* srai $dr,$uimm5 */
   {
     M32R_INSN_SRAI, "srai", "srai", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
   },
 /* srl $dr,$sr */
   {
     M32R_INSN_SRL, "srl", "srl", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
   },
 /* srl3 $dr,$sr,$simm16 */
   {
@@ -994,7 +1046,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* srli $dr,$uimm5 */
   {
     M32R_INSN_SRLI, "srli", "srli", 16,
-    { 0, { (1<<MACH_BASE), PIPE_O } }
+    { 0, { (1<<MACH_BASE), PIPE_O_OS } }
   },
 /* st $src1,@$src2 */
   {
@@ -1031,6 +1083,16 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
     M32R_INSN_ST_PLUS, "st-plus", "st", 16,
     { 0, { (1<<MACH_BASE), PIPE_O } }
   },
+/* sth $src1,@$src2+ */
+  {
+    M32R_INSN_STH_PLUS, "sth-plus", "sth", 16,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+  },
+/* stb $src1,@$src2+ */
+  {
+    M32R_INSN_STB_PLUS, "stb-plus", "stb", 16,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+  },
 /* st $src1,@-$src2 */
   {
     M32R_INSN_ST_MINUS, "st-minus", "st", 16,
@@ -1064,57 +1126,82 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 /* satb $dr,$sr */
   {
     M32R_INSN_SATB, "satb", "satb", 32,
-    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* sath $dr,$sr */
   {
     M32R_INSN_SATH, "sath", "sath", 32,
-    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* sat $dr,$sr */
   {
     M32R_INSN_SAT, "sat", "sat", 32,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* pcmpbz $src2 */
   {
     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
-    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
+    { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
   },
 /* sadd */
   {
     M32R_INSN_SADD, "sadd", "sadd", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* macwu1 $src1,$src2 */
   {
     M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* msblo $src1,$src2 */
   {
     M32R_INSN_MSBLO, "msblo", "msblo", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* mulwu1 $src1,$src2 */
   {
     M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* maclh1 $src1,$src2 */
   {
     M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
-    { 0, { (1<<MACH_M32RX), PIPE_S } }
+    { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* sc */
   {
     M32R_INSN_SC, "sc", "sc", 16,
-    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* snc */
   {
     M32R_INSN_SNC, "snc", "snc", 16,
-    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+  },
+/* clrpsw $uimm8 */
+  {
+    M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16,
+    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+  },
+/* setpsw $uimm8 */
+  {
+    M32R_INSN_SETPSW, "setpsw", "setpsw", 16,
+    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+  },
+/* bset $uimm3,@($slo16,$sr) */
+  {
+    M32R_INSN_BSET, "bset", "bset", 32,
+    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* bclr $uimm3,@($slo16,$sr) */
+  {
+    M32R_INSN_BCLR, "bclr", "bclr", 32,
+    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* btst $uimm3,$sr */
+  {
+    M32R_INSN_BTST, "btst", "btst", 16,
+    { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
   },
 };
 
diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h
index 8781772f26..ef61b69695 100644
--- a/opcodes/m32r-desc.h
+++ b/opcodes/m32r-desc.h
@@ -38,6 +38,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* Selected cpu families.  */
 #define HAVE_CPU_M32RBF
 #define HAVE_CPU_M32RXF
+#define HAVE_CPU_M32R2F
 
 #define CGEN_INSN_LSB0_P 0
 
@@ -90,18 +91,19 @@ typedef enum gr_names {
 /* Enum declaration for .  */
 typedef enum cr_names {
   H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
- , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_CR0 = 0
- , H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3, H_CR_CR4 = 4
- , H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7, H_CR_CR8 = 8
- , H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11, H_CR_CR12 = 12
- , H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
+ , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5
+ , H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3
+ , H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7
+ , H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11
+ , H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
 } CR_NAMES;
 
 /* Attributes.  */
 
 /* Enum declaration for machine type selection.  */
 typedef enum mach_attr {
-  MACH_BASE, MACH_M32R, MACH_M32RX, MACH_MAX
+  MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2
+ , MACH_MAX
 } MACH_ATTR;
 
 /* Enum declaration for instruction set selection.  */
@@ -112,6 +114,7 @@ typedef enum isa_attr {
 /* Enum declaration for parallel execution pipeline selection.  */
 typedef enum pipe_attr {
   PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
+ , PIPE_O_OS
 } PIPE_ATTR;
 
 /* Number of architecture variants.  */
@@ -138,11 +141,12 @@ typedef enum cgen_ifld_attr {
 typedef enum ifield_type {
   M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2
  , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8
- , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5
- , M32R_F_UIMM16, M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8
- , M32R_F_DISP16, M32R_F_DISP24, M32R_F_OP23, M32R_F_OP3
- , M32R_F_ACC, M32R_F_ACCS, M32R_F_ACCD, M32R_F_BITS67
- , M32R_F_BIT14, M32R_F_IMM1, M32R_F_MAX
+ , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3, M32R_F_UIMM4
+ , M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16, M32R_F_UIMM24
+ , M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16, M32R_F_DISP24
+ , M32R_F_OP23, M32R_F_OP3, M32R_F_ACC, M32R_F_ACCS
+ , M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4, M32R_F_BIT14
+ , M32R_F_IMM1, M32R_F_MAX
 } IFIELD_TYPE;
 
 #define MAX_IFLD ((int) M32R_F_MAX)
@@ -186,15 +190,16 @@ typedef enum cgen_operand_attr {
 typedef enum cgen_operand_type {
   M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
  , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
- , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
- , M32R_OPERAND_IMM1, M32R_OPERAND_ACCD, M32R_OPERAND_ACCS, M32R_OPERAND_ACC
- , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
- , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
- , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
+ , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5
+ , M32R_OPERAND_UIMM8, M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD
+ , M32R_OPERAND_ACCS, M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16
+ , M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8
+ , M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM
+ , M32R_OPERAND_MAX
 } CGEN_OPERAND_TYPE;
 
 /* Number of operands types.  */
-#define MAX_OPERANDS 26
+#define MAX_OPERANDS 28
 
 /* Maximum number of operands referenced by any insn.  */
 #define MAX_OPERAND_INSTANCES 11
@@ -206,8 +211,8 @@ typedef enum cgen_insn_attr {
   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL
- , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE
- , CGEN_INSN_END_NBOOLS
+ , CGEN_INSN_SPECIAL_M32R, CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
+ , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS
 } CGEN_INSN_ATTR;
 
 /* Number of non-boolean elements in cgen_insn_attr.  */
@@ -228,6 +233,7 @@ extern CGEN_KEYWORD m32r_cgen_opval_gr_names;
 extern CGEN_KEYWORD m32r_cgen_opval_cr_names;
 extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
 
+extern const CGEN_HW_ENTRY m32r_cgen_hw_table[];
 
 
 
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index e8abbc6134..6e5ea70ce9 100644
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -100,6 +100,8 @@ my_print_insn (cd, pc, info)
   char *buf = buffer;
   int status;
   int buflen = (pc & 3) == 0 ? 4 : 2;
+  int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
+  char *x;
 
   /* Read the base part of the insn.  */
 
@@ -111,22 +113,25 @@ my_print_insn (cd, pc, info)
     }
 
   /* 32 bit insn?  */
-  if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
+  x = (big_p ? &buf[0] : &buf[3]);
+  if ((pc & 3) == 0 && (*x & 0x80) != 0)
     return print_insn (cd, pc, info, buf, buflen);
 
   /* Print the first insn.  */
+  buf += (big_p ? 0 : 2);
   if ((pc & 3) == 0)
     {
       if (print_insn (cd, pc, info, buf, 2) == 0)
 	(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
-      buf += 2;
     }
+  buf += (big_p ? 2 : -2);
 
-  if (buf[0] & 0x80)
+  x = (big_p ? &buf[0] : &buf[1]);
+  if (*x & 0x80)
     {
       /* Parallel.  */
       (*info->fprintf_func) (info->stream, " || ");
-      buf[0] &= 0x7f;
+      *x &= 0x7f;
     }
   else
     (*info->fprintf_func) (info->stream, " -> ");
@@ -235,12 +240,18 @@ m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
     case M32R_OPERAND_UIMM24 :
       print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
       break;
+    case M32R_OPERAND_UIMM3 :
+      print_normal (cd, info, fields->f_uimm3, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
     case M32R_OPERAND_UIMM4 :
       print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
       break;
     case M32R_OPERAND_UIMM5 :
       print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
       break;
+    case M32R_OPERAND_UIMM8 :
+      print_normal (cd, info, fields->f_uimm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
     case M32R_OPERAND_ULO16 :
       print_normal (cd, info, fields->f_uimm16, 0, pc, length);
       break;
diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c
index 2a8d104e3f..32224da688 100644
--- a/opcodes/m32r-ibld.c
+++ b/opcodes/m32r-ibld.c
@@ -646,12 +646,18 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
     case M32R_OPERAND_UIMM24 :
       errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
       break;
+    case M32R_OPERAND_UIMM3 :
+      errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 5, 3, 32, total_length, buffer);
+      break;
     case M32R_OPERAND_UIMM4 :
       errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
       break;
     case M32R_OPERAND_UIMM5 :
       errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
       break;
+    case M32R_OPERAND_UIMM8 :
+      errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer);
+      break;
     case M32R_OPERAND_ULO16 :
       errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
       break;
@@ -779,12 +785,18 @@ m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
     case M32R_OPERAND_UIMM24 :
       length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
       break;
+    case M32R_OPERAND_UIMM3 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3);
+      break;
     case M32R_OPERAND_UIMM4 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
       break;
     case M32R_OPERAND_UIMM5 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
       break;
+    case M32R_OPERAND_UIMM8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8);
+      break;
     case M32R_OPERAND_ULO16 :
       length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
       break;
@@ -889,12 +901,18 @@ m32r_cgen_get_int_operand (cd, opindex, fields)
     case M32R_OPERAND_UIMM24 :
       value = fields->f_uimm24;
       break;
+    case M32R_OPERAND_UIMM3 :
+      value = fields->f_uimm3;
+      break;
     case M32R_OPERAND_UIMM4 :
       value = fields->f_uimm4;
       break;
     case M32R_OPERAND_UIMM5 :
       value = fields->f_uimm5;
       break;
+    case M32R_OPERAND_UIMM8 :
+      value = fields->f_uimm8;
+      break;
     case M32R_OPERAND_ULO16 :
       value = fields->f_uimm16;
       break;
@@ -979,12 +997,18 @@ m32r_cgen_get_vma_operand (cd, opindex, fields)
     case M32R_OPERAND_UIMM24 :
       value = fields->f_uimm24;
       break;
+    case M32R_OPERAND_UIMM3 :
+      value = fields->f_uimm3;
+      break;
     case M32R_OPERAND_UIMM4 :
       value = fields->f_uimm4;
       break;
     case M32R_OPERAND_UIMM5 :
       value = fields->f_uimm5;
       break;
+    case M32R_OPERAND_UIMM8 :
+      value = fields->f_uimm8;
+      break;
     case M32R_OPERAND_ULO16 :
       value = fields->f_uimm16;
       break;
@@ -1077,12 +1101,18 @@ m32r_cgen_set_int_operand (cd, opindex, fields, value)
     case M32R_OPERAND_UIMM24 :
       fields->f_uimm24 = value;
       break;
+    case M32R_OPERAND_UIMM3 :
+      fields->f_uimm3 = value;
+      break;
     case M32R_OPERAND_UIMM4 :
       fields->f_uimm4 = value;
       break;
     case M32R_OPERAND_UIMM5 :
       fields->f_uimm5 = value;
       break;
+    case M32R_OPERAND_UIMM8 :
+      fields->f_uimm8 = value;
+      break;
     case M32R_OPERAND_ULO16 :
       fields->f_uimm16 = value;
       break;
@@ -1163,12 +1193,18 @@ m32r_cgen_set_vma_operand (cd, opindex, fields, value)
     case M32R_OPERAND_UIMM24 :
       fields->f_uimm24 = value;
       break;
+    case M32R_OPERAND_UIMM3 :
+      fields->f_uimm3 = value;
+      break;
     case M32R_OPERAND_UIMM4 :
       fields->f_uimm4 = value;
       break;
     case M32R_OPERAND_UIMM5 :
       fields->f_uimm5 = value;
       break;
+    case M32R_OPERAND_UIMM8 :
+      fields->f_uimm8 = value;
+      break;
     case M32R_OPERAND_ULO16 :
       fields->f_uimm16 = value;
       break;
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index 8143b61852..18d8d68405 100644
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -30,6 +30,31 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #include "m32r-opc.h"
 #include "libiberty.h"
 
+/* -- opc.c */
+unsigned int
+m32r_cgen_dis_hash (buf, value)
+     const char * buf ATTRIBUTE_UNUSED;
+     CGEN_INSN_INT value;
+{
+  unsigned int x;
+                                                                                
+  if (value & 0xffff0000) /* 32bit instructions */
+    value = (value >> 16) & 0xffff;
+                                                                                
+  x = (value>>8) & 0xf0;
+  if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
+    return x;
+                                                                                
+  if (x == 0x70 || x == 0xf0)
+    return x | ((value>>8) & 0x0f);
+                                                                                
+  if (x == 0x30)
+    return x | ((value & 0x70) >> 4);
+  else
+    return x | ((value & 0xf0) >> 4);
+}
+                                                                                
+/* -- */
 /* The hash functions are recorded here to help keep assembler code out of
    the disassembler and vice versa.  */
 
@@ -173,6 +198,18 @@ static const CGEN_IFMT ifmt_satb = {
   32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
 };
 
+static const CGEN_IFMT ifmt_clrpsw = {
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bset = {
+  32, 32, 0xf8f00000, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_btst = {
+  16, 16, 0xf8f0, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
+};
+
 #undef F
 
 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
@@ -448,6 +485,48 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
     & ifmt_div, { 0x90300000 }
   },
+/* remh $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90200010 }
+  },
+/* remuh $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90300010 }
+  },
+/* remb $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90200018 }
+  },
+/* remub $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90300018 }
+  },
+/* divuh $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90100010 }
+  },
+/* divb $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90000018 }
+  },
+/* divub $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_div, { 0x90100018 }
+  },
 /* divh $dr,$sr */
   {
     { 0, 0, 0, 0 },
@@ -898,6 +977,18 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
     & ifmt_cmp, { 0x2060 }
   },
+/* sth $src1,@$src2+ */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
+    & ifmt_cmp, { 0x2030 }
+  },
+/* stb $src1,@$src2+ */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
+    & ifmt_cmp, { 0x2010 }
+  },
 /* st $src1,@-$src2 */
   {
     { 0, 0, 0, 0 },
@@ -1000,6 +1091,36 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, 0 } },
     & ifmt_nop, { 0x7501 }
   },
+/* clrpsw $uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (UIMM8), 0 } },
+    & ifmt_clrpsw, { 0x7200 }
+  },
+/* setpsw $uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (UIMM8), 0 } },
+    & ifmt_clrpsw, { 0x7100 }
+  },
+/* bset $uimm3,@($slo16,$sr) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+    & ifmt_bset, { 0xa0600000 }
+  },
+/* bclr $uimm3,@($slo16,$sr) */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+    & ifmt_bset, { 0xa0700000 }
+  },
+/* btst $uimm3,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (UIMM3), ',', OP (SR), 0 } },
+    & ifmt_btst, { 0xf0 }
+  },
 };
 
 #undef A
@@ -1202,12 +1323,12 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bcl $disp8 */
   {
     -1, "bcl8r", "bcl", 16,
-    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* bcl $disp24 */
   {
     -1, "bcl24r", "bcl", 32,
-    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* bnc $disp8 */
   {
@@ -1232,12 +1353,12 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* bncl $disp8 */
   {
     -1, "bncl8r", "bncl", 16,
-    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
+    { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
   },
 /* bncl $disp24 */
   {
     -1, "bncl24r", "bncl", 32,
-    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
+    { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
   },
 /* ld $dr,@($sr) */
   {
@@ -1307,22 +1428,22 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* rac $accd */
   {
     -1, "rac-d", "rac", 16,
-    { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* rac $accd,$accs */
   {
     -1, "rac-ds", "rac", 16,
-    { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* rach $accd */
   {
     -1, "rach-d", "rach", 16,
-    { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* rach $accd,$accs */
   {
     -1, "rach-ds", "rach", 16,
-    { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+    { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
   },
 /* st $src1,@($src2) */
   {
@@ -1357,7 +1478,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
 /* push $src1 */
   {
     -1, "push", "push", 16,
-    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+    { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
   },
 };
 
diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h
index 22e6924b06..5fe7106528 100644
--- a/opcodes/m32r-opc.h
+++ b/opcodes/m32r-opc.h
@@ -30,6 +30,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #undef  CGEN_DIS_HASH_SIZE
 #define CGEN_DIS_HASH_SIZE 256
 #undef  CGEN_DIS_HASH
+#if 0
 #define X(b) (((unsigned char *) (b))[0] & 0xf0)
 #define CGEN_DIS_HASH(buffer, value) \
 (X (buffer) | \
@@ -37,6 +38,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
   : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
   : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
   : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
+#else
+#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value)
+extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT);
+#endif
 
 /* -- */
 /* Enum declaration for m32r instruction types.  */
@@ -51,37 +56,41 @@ typedef enum cgen_insn_type {
  , M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA24, M32R_INSN_BNCL8
  , M32R_INSN_BNCL24, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU
  , M32R_INSN_CMPUI, M32R_INSN_CMPEQ, M32R_INSN_CMPZ, M32R_INSN_DIV
- , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_DIVH
- , M32R_INSN_JC, M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP
- , M32R_INSN_LD, M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D
- , M32R_INSN_LDH, M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D
- , M32R_INSN_LDUH, M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24
- , M32R_INSN_LDI8, M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI
- , M32R_INSN_MACHI_A, M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI
- , M32R_INSN_MACWHI_A, M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL
- , M32R_INSN_MULHI, M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A
- , M32R_INSN_MULWHI, M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A
- , M32R_INSN_MV, M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO
- , M32R_INSN_MVFACLO_A, M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC
- , M32R_INSN_MVTACHI, M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A
- , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
- , M32R_INSN_RAC, M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI
- , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3
- , M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI
- , M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST
- , M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH
- , M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB
- , M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK
- , M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT, M32R_INSN_PCMPBZ
- , M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO, M32R_INSN_MULWU1
- , M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC
+ , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_REMH
+ , M32R_INSN_REMUH, M32R_INSN_REMB, M32R_INSN_REMUB, M32R_INSN_DIVUH
+ , M32R_INSN_DIVB, M32R_INSN_DIVUB, M32R_INSN_DIVH, M32R_INSN_JC
+ , M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD
+ , M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH
+ , M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH
+ , M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8
+ , M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACHI_A
+ , M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI, M32R_INSN_MACWHI_A
+ , M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL, M32R_INSN_MULHI
+ , M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A, M32R_INSN_MULWHI
+ , M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A, M32R_INSN_MV
+ , M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO, M32R_INSN_MVFACLO_A
+ , M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC, M32R_INSN_MVTACHI
+ , M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A, M32R_INSN_MVTC
+ , M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC
+ , M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI, M32R_INSN_RTE
+ , M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3, M32R_INSN_SLLI
+ , M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI, M32R_INSN_SRL
+ , M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST, M32R_INSN_ST_D
+ , M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH, M32R_INSN_STH_D
+ , M32R_INSN_ST_PLUS, M32R_INSN_STH_PLUS, M32R_INSN_STB_PLUS, M32R_INSN_ST_MINUS
+ , M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP
+ , M32R_INSN_UNLOCK, M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT
+ , M32R_INSN_PCMPBZ, M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO
+ , M32R_INSN_MULWU1, M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC
+ , M32R_INSN_CLRPSW, M32R_INSN_SETPSW, M32R_INSN_BSET, M32R_INSN_BCLR
+ , M32R_INSN_BTST
 } CGEN_INSN_TYPE;
 
 /* Index of `invalid' insn place holder.  */
 #define CGEN_INSN_INVALID M32R_INSN_INVALID
 
 /* Total number of insns in table.  */
-#define MAX_INSNS ((int) M32R_INSN_SNC + 1)
+#define MAX_INSNS ((int) M32R_INSN_BTST + 1)
 
 /* This struct records data prior to insertion or after extraction.  */
 struct cgen_fields
@@ -97,8 +106,10 @@ struct cgen_fields
   long f_simm8;
   long f_simm16;
   long f_shift_op2;
+  long f_uimm3;
   long f_uimm4;
   long f_uimm5;
+  long f_uimm8;
   long f_uimm16;
   long f_uimm24;
   long f_hi16;
@@ -111,6 +122,7 @@ struct cgen_fields
   long f_accs;
   long f_accd;
   long f_bits67;
+  long f_bit4;
   long f_bit14;
   long f_imm1;
 };
diff --git a/opcodes/m32r-opinst.c b/opcodes/m32r-opinst.c
index 5365d15a73..370aa7c0a8 100644
--- a/opcodes/m32r-opinst.c
+++ b/opcodes/m32r-opinst.c
@@ -42,42 +42,42 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #define COND_REF CGEN_OPINST_COND_REF
 
 static const CGEN_OPINST sfmt_empty_ops[] = {
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_add_ops[] = {
   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_add3_ops[] = {
   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_and3_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_or3_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_addi_ops[] = {
   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
   { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_addv_ops[] = {
@@ -85,7 +85,7 @@ static const CGEN_OPINST sfmt_addv_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_addv3_ops[] = {
@@ -93,7 +93,7 @@ static const CGEN_OPINST sfmt_addv3_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_addx_ops[] = {
@@ -102,21 +102,21 @@ static const CGEN_OPINST sfmt_addx_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bc8_ops[] = {
   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bc24_ops[] = {
   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_beq_ops[] = {
@@ -124,14 +124,14 @@ static const CGEN_OPINST sfmt_beq_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_beqz_ops[] = {
   { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bl8_ops[] = {
@@ -139,7 +139,7 @@ static const CGEN_OPINST sfmt_bl8_ops[] = {
   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bl24_ops[] = {
@@ -147,7 +147,7 @@ static const CGEN_OPINST sfmt_bl24_ops[] = {
   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bcl8_ops[] = {
@@ -156,7 +156,7 @@ static const CGEN_OPINST sfmt_bcl8_ops[] = {
   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bcl24_ops[] = {
@@ -165,53 +165,53 @@ static const CGEN_OPINST sfmt_bcl24_ops[] = {
   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bra8_ops[] = {
   { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_bra24_ops[] = {
   { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_cmp_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_cmpi_ops[] = {
   { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_cmpz_ops[] = {
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_div_ops[] = {
   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_jc_ops[] = {
   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_jl_ops[] = {
@@ -219,20 +219,20 @@ static const CGEN_OPINST sfmt_jl_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_jmp_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ld_ops[] = {
   { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ld_d_ops[] = {
@@ -240,14 +240,14 @@ static const CGEN_OPINST sfmt_ld_d_ops[] = {
   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ldb_ops[] = {
   { INPUT, "h_memory_QI_sr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ldb_d_ops[] = {
@@ -255,14 +255,14 @@ static const CGEN_OPINST sfmt_ldb_d_ops[] = {
   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ldh_ops[] = {
   { INPUT, "h_memory_HI_sr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ldh_d_ops[] = {
@@ -270,7 +270,7 @@ static const CGEN_OPINST sfmt_ldh_d_ops[] = {
   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ld_plus_ops[] = {
@@ -278,25 +278,25 @@ static const CGEN_OPINST sfmt_ld_plus_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
   { OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ld24_ops[] = {
   { INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ldi8_ops[] = {
   { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_ldi16_ops[] = {
   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_lock_ops[] = {
@@ -304,7 +304,7 @@ static const CGEN_OPINST sfmt_lock_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
   { OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_machi_ops[] = {
@@ -312,7 +312,7 @@ static const CGEN_OPINST sfmt_machi_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_machi_a_ops[] = {
@@ -320,82 +320,82 @@ static const CGEN_OPINST sfmt_machi_a_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mulhi_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mulhi_a_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mv_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mvfachi_ops[] = {
   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mvfachi_a_ops[] = {
   { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mvfc_ops[] = {
   { INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mvtachi_ops[] = {
   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mvtachi_a_ops[] = {
   { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { OUTPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mvtc_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_nop_ops[] = {
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_rac_ops[] = {
   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_rac_dsi_ops[] = {
   { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
   { INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 },
   { OUTPUT, "accd", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCD), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_rte_ops[] = {
@@ -407,34 +407,34 @@ static const CGEN_OPINST sfmt_rte_ops[] = {
   { OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
   { OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_seth_ops[] = {
   { INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_sll3_ops[] = {
   { INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_slli_ops[] = {
   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
   { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_st_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_st_d_ops[] = {
@@ -442,14 +442,14 @@ static const CGEN_OPINST sfmt_st_d_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_SI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_stb_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_QI_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_stb_d_ops[] = {
@@ -457,14 +457,14 @@ static const CGEN_OPINST sfmt_stb_d_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_QI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_sth_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_HI_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_sth_d_ops[] = {
@@ -472,7 +472,7 @@ static const CGEN_OPINST sfmt_sth_d_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_HI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_st_plus_ops[] = {
@@ -480,7 +480,23 @@ static const CGEN_OPINST sfmt_st_plus_ops[] = {
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_memory_SI_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
   { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_sth_plus_ops[] = {
+  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "h_memory_HI_new_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+  { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_stb_plus_ops[] = {
+  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "h_memory_QI_new_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_trap_ops[] = {
@@ -495,7 +511,7 @@ static const CGEN_OPINST sfmt_trap_ops[] = {
   { OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
   { OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_unlock_ops[] = {
@@ -504,27 +520,27 @@ static const CGEN_OPINST sfmt_unlock_ops[] = {
   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF },
   { OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
   { OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_satb_ops[] = {
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_sat_ops[] = {
   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_sadd_ops[] = {
   { INPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
   { INPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
   { OUTPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_macwu1_ops[] = {
@@ -532,19 +548,48 @@ static const CGEN_OPINST sfmt_macwu1_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_mulwu1_ops[] = {
   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
   { OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 static const CGEN_OPINST sfmt_sc_ops[] = {
   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
-  { END }
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_clrpsw_ops[] = {
+  { INPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
+  { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_BI, OP_ENT (UIMM8), 0, 0 },
+  { OUTPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_setpsw_ops[] = {
+  { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_USI, OP_ENT (UIMM8), 0, 0 },
+  { OUTPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_bset_ops[] = {
+  { INPUT, "h_memory_QI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
+  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
+  { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
+  { OUTPUT, "h_memory_QI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_btst_ops[] = {
+  { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
+  { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
+  { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
 };
 
 #undef OP_ENT
@@ -600,6 +645,13 @@ static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
   & sfmt_div_ops[0],
   & sfmt_div_ops[0],
   & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
+  & sfmt_div_ops[0],
   & sfmt_jc_ops[0],
   & sfmt_jc_ops[0],
   & sfmt_jl_ops[0],
@@ -674,6 +726,8 @@ static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
   & sfmt_sth_ops[0],
   & sfmt_sth_d_ops[0],
   & sfmt_st_plus_ops[0],
+  & sfmt_sth_plus_ops[0],
+  & sfmt_stb_plus_ops[0],
   & sfmt_st_plus_ops[0],
   & sfmt_add_ops[0],
   & sfmt_addv_ops[0],
@@ -691,6 +745,11 @@ static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
   & sfmt_macwu1_ops[0],
   & sfmt_sc_ops[0],
   & sfmt_sc_ops[0],
+  & sfmt_clrpsw_ops[0],
+  & sfmt_setpsw_ops[0],
+  & sfmt_bset_ops[0],
+  & sfmt_bset_ops[0],
+  & sfmt_btst_ops[0],
 };
 
 /* Function to call before using the operand instance table.  */