* s390-dis.c (print_insn_s390): Print unsigned operands with %u.

	* s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
	(main): Likewise.
	* s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
	and 4 bit optional masks.
	(INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
	INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
	(MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
	MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
	(s390_opformats): Likewise.
	* s390-opc.txt: Add new instructions for cpu type z9-109.

5 files changed, 109 insertions, 12 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 22add3b8b7..e9fa2be224 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,17 @@
+2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390-dis.c (print_insn_s390): Print unsigned operands with %u.
+	* s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
+	(main): Likewise.
+	* s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
+	and 4 bit optional masks.
+	(INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
+	INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
+	(MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
+	MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
+	(s390_opformats): Likewise.
+	* s390-opc.txt: Add new instructions for cpu type z9-109.
+
 2005-08-05  John David Anglin  <dave.anglin@nrc-crnc.gc.ca>
 
 	* hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%".
diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c
index 013c75a3f7..9b0a063b93 100644
--- a/opcodes/s390-dis.c
+++ b/opcodes/s390-dis.c
@@ -206,7 +206,7 @@ print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
 	      else if (operand->flags & S390_OPERAND_SIGNED)
 		(*info->fprintf_func) (info->stream, "%i", (int) value);
 	      else
-		(*info->fprintf_func) (info->stream, "%i", value);
+		(*info->fprintf_func) (info->stream, "%u", value);
 
 	      if (operand->flags & S390_OPERAND_DISP)
 		{
diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c
index 8a326300d7..5a794fdd5d 100644
--- a/opcodes/s390-mkopc.c
+++ b/opcodes/s390-mkopc.c
@@ -35,7 +35,8 @@ enum s390_opcode_cpu_val
     S390_OPCODE_G5 = 0,
     S390_OPCODE_G6,
     S390_OPCODE_Z900,
-    S390_OPCODE_Z990
+    S390_OPCODE_Z990,
+    S390_OPCODE_Z9_109
   };
 
 struct op_struct
@@ -195,6 +196,8 @@ main (void)
 	    min_cpu = S390_OPCODE_Z900;
 	  else if (strcmp (cpu_string, "z990") == 0)
 	    min_cpu = S390_OPCODE_Z990;
+	  else if (strcmp (cpu_string, "z9-109") == 0)
+	    min_cpu = S390_OPCODE_Z9_109;
 	  else {
 	    fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);
 	    exit (1);
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 4c5200380a..aa2e5a35ad 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -127,7 +127,13 @@ const struct s390_operand s390_operands[] =
 #define J16_16 38                 /* PC relative jump offset at 16 */
   { 16, 16, S390_OPERAND_PCREL },
 #define J32_16 39                 /* PC relative long offset at 16 */
-  { 32, 16, S390_OPERAND_PCREL }
+  { 32, 16, S390_OPERAND_PCREL },
+#define I32_16 40		  /* 32 bit signed value starting at 16 */
+  { 32, 16, S390_OPERAND_SIGNED },
+#define U32_16 41		  /* 32 bit unsigned value starting at 16 */
+  { 32, 16, 0 },
+#define M_16   42                 /* 4 bit optional mask starting at 16 */
+  { 4, 16, S390_OPERAND_OPTIONAL }
 };
 
 
@@ -151,11 +157,12 @@ const struct s390_operand s390_operands[] =
       c - control register
       d - displacement, 12 bit
       f - floating pointer register
-      i - signed integer, 4 or 8 bit
+      i - signed integer, 4, 8, 16 or 32 bit
       l - length, 4 or 8 bit
       p - pc relative
       r - general purpose register
-      u - unsigned integer, 4 or 8 bit
+      u - unsigned integer, 4, 8, 16 or 32 bit
+      m - mode field, 4 bit
       0 - operand skipped.
       The order of the letters reflects the layout of the format in
       storage and not the order of the paramaters of the instructions.
@@ -178,6 +185,8 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RIL_0P     6, { J32_16,0,0,0,0 }                 /* e.g. jg    */
 #define INSTR_RIL_RP     6, { R_8,J32_16,0,0,0,0 }             /* e.g. brasl */
 #define INSTR_RIL_UP     6, { U4_8,J32_16,0,0,0,0 }            /* e.g. brcl  */
+#define INSTR_RIL_RI     6, { R_8,I32_16,0,0,0,0 }             /* e.g. afi   */
+#define INSTR_RIL_RU     6, { R_8,U32_16,0,0,0,0 }             /* e.g. alfi  */
 #define INSTR_RI_0P      4, { J16_16,0,0,0,0,0 }               /* e.g. j     */
 #define INSTR_RI_RI      4, { R_8,I16_16,0,0,0,0 }             /* e.g. ahi   */
 #define INSTR_RI_RP      4, { R_8,J16_16,0,0,0,0 }             /* e.g. brct  */
@@ -200,6 +209,7 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RRF_U0FF   4, { F_24,U4_16,F_28,0,0,0 }          /* e.g. cfxbr */
 #define INSTR_RRF_U0FR   4, { F_24,U4_16,R_28,0,0,0 }          /* e.g. cfebr */
 #define INSTR_RRF_U0FR   4, { F_24,U4_16,R_28,0,0,0 }          /* e.g. cfxbr */
+#define INSTR_RRF_M0RR   4, { R_24,R_28,M_16,0,0,0 }           /* e.g. sske  */
 #define INSTR_RR_0R      2, { R_12, 0,0,0,0,0 }                /* e.g. br    */
 #define INSTR_RR_FF      2, { F_8,F_12,0,0,0,0 }               /* e.g. adr   */
 #define INSTR_RR_R0      2, { R_8, 0,0,0,0,0 }                 /* e.g. spm   */
@@ -207,12 +217,14 @@ const struct s390_operand s390_operands[] =
 #define INSTR_RR_U0      2, { U8_8, 0,0,0,0,0 }                /* e.g. svc   */
 #define INSTR_RR_UR      2, { U4_8,R_12,0,0,0,0 }              /* e.g. bcr   */
 #define INSTR_RSE_RRRD   6, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. lmh   */
+#define INSTR_RSE_CCRD   6, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lmh   */
 #define INSTR_RSE_RURD   6, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icmh  */
 #define INSTR_RSL_R0RD   6, { R_8,D_20,B_16,0,0,0 }            /* e.g. tp    */
 #define INSTR_RSI_RRP    4, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxh  */
 #define INSTR_RSY_RRRD   6, { R_8,R_12,D20_20,B_16,0,0 }       /* e.g. stmy  */
 #define INSTR_RSY_RURD   6, { R_8,U4_12,D20_20,B_16,0,0 }      /* e.g. icmh  */
 #define INSTR_RSY_AARD   6, { A_8,A_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
+#define INSTR_RSY_CCRD   6, { C_8,C_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
 #define INSTR_RS_AARD    4, { A_8,A_12,D_20,B_16,0,0 }         /* e.g. lam   */
 #define INSTR_RS_CCRD    4, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lctl  */
 #define INSTR_RS_R0RD    4, { R_8,D_20,B_16,0,0,0 }            /* e.g. sll   */
@@ -239,12 +251,15 @@ const struct s390_operand s390_operands[] =
 #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 }   /* e.g. lmd   */
 #define INSTR_S_00       4, { 0,0,0,0,0,0 }                    /* e.g. hsch  */
 #define INSTR_S_RD       4, { D_20,B_16,0,0,0,0 }              /* e.g. lpsw  */
+#define INSTR_SSF_RRDRD  6, { D_20,B_16,D_36,B_32,R_8,0 }      /* e.g. mvcos */
 
 #define MASK_E           { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RIE_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RIL_0P      { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RIL_RP      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RIL_UP      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RIL_RI      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RIL_RU      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RI_0P       { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RI_RI       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RI_RP       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
@@ -267,6 +282,7 @@ const struct s390_operand s390_operands[] =
 #define MASK_RRF_U0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0FR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RRF_U0FR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
+#define MASK_RRF_M0RR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
 #define MASK_RR_0R       { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_FF       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_R0       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
@@ -274,6 +290,7 @@ const struct s390_operand s390_operands[] =
 #define MASK_RR_U0       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_UR       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RSE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSE_CCRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSE_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSL_R0RD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSI_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
@@ -285,6 +302,7 @@ const struct s390_operand s390_operands[] =
 #define MASK_RSY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSY_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RSY_AARD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSY_CCRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXE_FRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
 #define MASK_RXF_FRRDF   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
@@ -306,6 +324,7 @@ const struct s390_operand s390_operands[] =
 #define MASK_SS_RRRDRD3  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_S_00        { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
 #define MASK_S_RD        { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_SSF_RRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 
 /* The opcode formats table (blueprints for .insn pseudo mnemonic).  */
 
@@ -315,6 +334,7 @@ const struct s390_opcode s390_opformats[] =
   { "ri",	OP8(0x00LL),	MASK_RI_RI,	INSTR_RI_RI,	3, 0 },
   { "rie",	OP8(0x00LL),	MASK_RIE_RRP,	INSTR_RIE_RRP,	3, 0 },
   { "ril",	OP8(0x00LL),	MASK_RIL_RP,	INSTR_RIL_RP,	3, 0 },
+  { "rilu",	OP8(0x00LL),	MASK_RIL_RU,	INSTR_RIL_RU,	3, 0 },
   { "rr",	OP8(0x00LL),	MASK_RR_RR,	INSTR_RR_RR,	3, 0 },
   { "rre",	OP8(0x00LL),	MASK_RRE_RR,	INSTR_RRE_RR,	3, 0 },
   { "rrf",	OP8(0x00LL),	MASK_RRF_RURR,	INSTR_RRF_RURR,	3, 0 },
@@ -331,6 +351,7 @@ const struct s390_opcode s390_opformats[] =
   { "siy",	OP8(0x00LL),	MASK_SIY_URD,	INSTR_SIY_URD,	3, 3 },
   { "ss",	OP8(0x00LL),	MASK_SS_RRRDRD,	INSTR_SS_RRRDRD,3, 0 },
   { "sse",	OP8(0x00LL),	MASK_SSE_RDRD,	INSTR_SSE_RDRD,	3, 0 },
+  { "ssf",	OP8(0x00LL),	MASK_SSF_RRDRD,	INSTR_SSF_RRDRD,3, 0 },
 };
 
 const int s390_num_opformats =
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 80e746a42e..fdec73573e 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -464,7 +464,7 @@ b920 cgr RRE_RR "compare 64" z900 zarch
 b930 cgfr RRE_RR "compare 64<32" z900 zarch
 b908 agr RRE_RR "add 64" z900 zarch
 b918 agfr RRE_RR "add 64<32" z900 zarch
-b909 sgr RRE_RR "subtract 64" z900 zarch zarch
+b909 sgr RRE_RR "subtract 64" z900 zarch
 b919 sgfr RRE_RR "subtract 64<32" z900 zarch
 b90a algr RRE_RR "add logical 64" z900 zarch
 b91a algfr RRE_RR "add logical 64<32" z900 zarch
@@ -510,8 +510,8 @@ ef lmd SS_RRRDRD3 "load multiple disjoint" z900 zarch
 eb000000000f tracg RSE_RRRD "trace 64" z900 zarch
 e30000000003 lrag RXE_RRRD "load real address 64" z900 zarch
 e50000000002 strag SSE_RDRD "store read address" z900 zarch
-eb0000000025 stctg RSE_RRRD "store control 64" z900 zarch
-eb000000002f lctlg RSE_RRRD "load control 64" z900 zarch
+eb0000000025 stctg RSE_CCRD "store control 64" z900 zarch
+eb000000002f lctlg RSE_CCRD "load control 64" z900 zarch
 eb0000000030 csg RSE_RRRD "compare and swap 64" z900 zarch
 eb000000003e cdsg RSE_RRRD "compare double and swap 64" z900 zarch
 eb0000000020 clmh RSE_RURD "compare logical characters under mask high" z900 zarch
@@ -648,7 +648,6 @@ ed0000000024 lde RXE_FRRD "load lengthened short to long hfp" g5 esa,zarch
 b361 lnxr RRE_FF "load negative long hfp" g5 esa,zarch
 b360 lpxr RRE_FF "load positive long hfp" g5 esa,zarch
 b366 lexr RRE_FF "load rounded extended to short hfp" g5 esa,zarch
-35 ledr RR_FF "load rounded long to short hfp" g5 esa,zarch
 b337 meer RRE_FF "multiply short hfp" g5 esa,zarch
 ed0000000037 mee RXE_FRRD "multiply short hfp" g5 esa,zarch
 b336 sqxr RRE_FF "square root extended hfp" g5 esa,zarch
@@ -763,10 +762,10 @@ eb000000001c rllg RSY_RRRD "rotate left single logical 64" z990 zarch
 eb000000001d rll RSY_RRRD "rotate left single logical 32" z990 esa,zarch
 eb0000000020 clmh RSY_RURD "compare logical characters under mask high with long offset" z990 zarch
 eb0000000024 stmg RSY_RRRD "store multiple with long offset 64" z990 zarch
-eb0000000025 stctg RSY_RRRD "store control 64" z990 zarch
+eb0000000025 stctg RSY_CCRD "store control 64" z990 zarch
 eb0000000026 stmh RSY_RRRD "store multiple high" z990 zarch
 eb000000002c stcmh RSY_RURD "store characters under mask high with long offset" z990 zarch
-eb000000002f lctlg RSY_RRRD "load control 64" z990 zarch
+eb000000002f lctlg RSY_CCRD "load control 64" z990 zarch
 eb0000000030 csg RSY_RRRD "compare and swap with long offset 64" z990 zarch
 eb000000003e cdsg RSY_RRRD "compare double and swap with long offset 64" z990 zarch
 eb0000000044 bxhg RSY_RRRD "branch on index high 64" z990 zarch
@@ -781,7 +780,7 @@ b98e idte RRF_R0RR "invalidate dat table entry" z990 zarch
 b33e madr RRF_F0FF "multiply and add long hfp" z990 esa,zarch
 ed000000003e mad RXF_FRRDF "multiply and add long hfp" z990 esa,zarch
 b32e maer RRF_F0FF "multiply and add short hfp" z990 esa,zarch
-ed000000002e mae RXF_FRRDF "multiply and add shoft hfp" z990 esa,zarch
+ed000000002e mae RXF_FRRDF "multiply and add short hfp" z990 esa,zarch
 b33f msdr RRF_F0FF "multiply and subtract long hfp" z990 esa,zarch
 ed000000003f msd RXF_FRRDF "multiply and subtract long hfp" z990 esa,zarch
 b32f mser RRF_F0FF "mutliply and subtract short hfp" z990 esa,zarch
@@ -791,3 +790,63 @@ b92f kmc RRE_RR "cipher message with chaining" z990 esa,zarch
 b93e kimd RRE_RR "compute intermediate message digest" z990 esa,zarch
 b93f klmd RRE_RR "compute last message digest" z990 esa,zarch
 b91e kmac RRE_RR "compute message authentication code" z990 esa,zarch
+# z9-109 extended immediate instructions
+c209 afi RIL_RI "add immediate 32" z9-109 zarch
+c208 agfi RIL_RI "add immediate 64<32" z9-109 zarch
+c20b alfi RIL_RU "add logical immediate 32" z9-109 zarch
+c20a algfi RIL_RU "add logical immediate 64<32" z9-109 zarch
+c00a nihf RIL_RU "and immediate high" z9-109 zarch
+c00b nilf RIL_RU "and immediate low" z9-109 zarch
+c20d cfi RIL_RI "compare immediate 32" z9-109 zarch
+c20c cgfi RIL_RI "compare immediate 64<32" z9-109 zarch
+c20f clfi RIL_RU "compare logical immediate 32" z9-109 zarch
+c20e clgfi RIL_RU "compare logical immediate 64<32" z9-109 zarch
+c006 xihf RIL_RU "exclusive or immediate high" z9-109 zarch
+c007 xilf RIL_RU "exclusive or immediate low" z9-109 zarch
+c008 iihf RIL_RU "insert immediate high" z9-109 zarch
+c009 iilf RIL_RU "insert immediate low" z9-109 zarch
+# z9-109 misc instruction
+b983 flogr RRE_RR "find leftmost one" z9-109 zarch
+e30000000012 lt RXY_RRRD "load and test 32" z9-109 zarch
+e30000000002 ltg RXY_RRRD "load and test 64" z9-109 zarch
+b926 lbr RRE_RR "load byte 32" z9-109 zarch
+b906 lgbr RRE_RR "load byte 64" z9-109 zarch
+b927 lhr RRE_RR "load halfword 32" z9-109 zarch
+b907 lghr RRE_RR "load halfword 64" z9-109 zarch
+c001 lgfi RIL_RI "load immediate 64<32" z9-109 zarch
+e30000000094 llc RXY_RRRD "load logical character 32" z9-109 zarch
+b994 llcr RRE_RR "load logical character 32" z9-109 zarch
+b984 llgcr RRE_RR "load logical character 64" z9-109 zarch
+e30000000095 llh RXY_RRRD "load logical halfword 32" z9-109 zarch
+b995 llhr RRE_RR "load logical halfword 32" z9-109 zarch
+b985 llghr RRE_RR "load logical halfword 64" z9-109 zarch
+c00e llihf RIL_RU "load logical immediate high" z9-109 zarch
+c00f llilf RIL_RU "load logical immediate low" z9-109 zarch
+c00c oihf RIL_RU "or immediate high" z9-109 zarch
+c00d oilf RIL_RU "or immediate low" z9-109 zarch
+c205 slfi RIL_RU "subtract logical immediate 32" z9-109 zarch
+c204 slgfi RIL_RU "subtract logical immediate 64<32" z9-109 zarch
+# z9-109 store facility list extended
+b2b0 stfle S_RD "store facility list extended" z9-109 zarch
+# z9-109 store clock fast
+b27c stckf S_RD "store clock fast" z9-109 zarch
+# z9-109 move with optional specifications instruction
+c800 mvcos SSF_RRDRD "move with optional specifications" z9-109 zarch
+# z9-109 load page-table-entry address instruction
+b9aa lptea RRF_RURR "load page-table-entry address" z9-109 zarch
+# z9-109 conditional sske facility, sske instruction entered twice
+b22b sske RRF_M0RR "set storage key extended" z9-109 zarch
+# z9-109 etf2-enhancement facility, instructions entered twice
+b993 troo RRF_M0RR "translate one to one" z9-109 esa,zarch
+b992 trot RRF_M0RR "translate one to two" z9-109 esa,zarch
+b991 trto RRF_M0RR "translate two to one" z9-109 esa,zarch
+b990 trtt RRF_M0RR "translate two to two" z9-109 esa,zarch
+# z9-109 etf3-enhancement facility, some instructions entered twice
+b9b1 cu24 RRF_M0RR "convert utf-16 to utf-32" z9-109 zarch
+b2a6 cu21 RRF_M0RR "convert utf-16 to utf-8" z9-109 zarch
+b2a6 cuutf RRF_M0RR "convert unicode to utf-8" z9-109 zarch
+b9b3 cu42 RRF_M0RR "convert utf-32 to utf-16" z9-109 zarch
+b9b2 cu41 RRF_M0RR "convert utf-32 to utf-8" z9-109 zarch
+b2a7 cu12 RRF_M0RR "convert utf-8 to utf-16" z9-109 zarch
+b2a7 cutfu RRF_M0RR "convert utf-8 to unicode" z9-109 zarch
+b9b0 cu14 RRF_M0RR "convert utf-8 to utf-32" z9-109 zarch