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authorRichard Sandiford <rsandifo@nildram.co.uk>2013-07-07 11:32:30 +0000
committerRichard Sandiford <rsandifo@nildram.co.uk>2013-07-07 11:32:30 +0000
commite6d68268b1662adc1f14738204366e6c73ed9278 (patch)
treed6bcf7aade01458f298c1122e795d9594a46dfd7 /opcodes
parented24d84c8df7574481f5c7e2eef0766396c32687 (diff)
downloadbinutils-redhat-e6d68268b1662adc1f14738204366e6c73ed9278.tar.gz
include/opcode/
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): Rename to... (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) (M_USD_AB): ...these. opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD and SD A(B) macros up. * micromips-opc.c (micromips_opcodes): Likewise. gas/ * config/tc-mips.c (gprel16_reloc_p): New function. (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are BFD_RELOC_UNUSED. (offset_high_part, small_offset_p): New functions. (nacro): Use them. Remove *_OB and *_DOB cases. For single- register load and store macros, handle the 16-bit offset case first. If a 16-bit offset is not suitable for the instruction we're generating, load it into the temporary register using ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the M_L_DAB code once the address has been constructed. For double load and store macros, again handle the 16-bit offset case first. If the second register cannot be accessed from the same high part as the first, load it into AT using ADDRESS_ADDI_INSN. Fix the handling of LD in cases where the first register is the same as the base. Also handle the case where the offset is not 16 bits and the second register cannot be accessed from the same high part as the first. For unaligned loads and stores, fuse the offbits == 12 and old "ab" handling. Apply this handling whenever the second offset needs a different high part from the first. Construct the offset using ADDRESS_ADDI_INSN where possible, for offbits == 16 as well as offbits == 12. Use offset_reloc when constructing the individual loads and stores. (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc and offset_reloc before matching against a particular opcode. Handle elided 'A' constants. Allow 'A' constants to use relocation operators. gas/testsuite/ * gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for truncated constants. * gas/mips/ldstla-32-shared.d: Likewise. * gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding 16-bit constants to the base. * gas/mips/micromips@mcu.d: Likewise. * gas/mips/micromips@cache.d: Likewise. * gas/mips/micromips@pref.d: Likewise. * gas/mips/micromips.d, gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise. Allow the full 16-bit offset range to be used for SB, LB and LBU in USH and ULH sequences. Fix the expected output for LD and SD when the two LW and SW offsets need different high parts. * gas/mips/eva.s: Test PREFE with relocation operators. * gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit constants. Update after eva.s change. * gas/mips/micromips@eva.d: Likewise. * gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s, gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d, gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s, gas/mips/ulh-reloc.d: New tests. * gas/mips/mips.exp: Run them.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/micromips-opc.c76
-rw-r--r--opcodes/mips-opc.c49
3 files changed, 24 insertions, 107 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fe6a543c58..88dd9728fb 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,11 @@
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+ * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
+ and SD A(B) macros up.
+ * micromips-opc.c (micromips_opcodes): Likewise.
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
* mips16-opc.c: Add entries for argumentless "entry" and "exit"
instructions.
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 6a7239629d..de8053c5ed 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -127,7 +127,6 @@ const struct mips_opcode micromips_opcodes[] =
instruction name anyhow. */
/* name, args, match, mask, pinfo, pinfo2, membership, [ase], [exclusions] */
{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_b, 0, I1 },
-{"pref", "k,o(b)", 0, (int) M_PREF_OB, INSN_MACRO, 0, I1 },
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1 },
{"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I1 },
{"nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS, I1 },
@@ -160,7 +159,6 @@ const struct mips_opcode micromips_opcodes[] =
{"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
{"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
{"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, SM|RD_b|NODS, 0, 0, MC },
-{"aclr", "\\,o(b)", 0, (int) M_ACLR_OB, INSN_MACRO, 0, 0, MC },
{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC },
{"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
@@ -195,7 +193,6 @@ const struct mips_opcode micromips_opcodes[] =
{"andi", "md,mc,mC", 0x2c00, 0xfc00, 0, WR_md|RD_mc, I1 },
{"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"aset", "\\,~(b)", 0x20003000, 0xff00f000, SM|RD_b|NODS, 0, 0, MC },
-{"aset", "\\,o(b)", 0, (int) M_ASET_OB, INSN_MACRO, 0, 0, MC },
{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC },
/* b is at the top of the table. */
/* bal is at the top of the table. */
@@ -383,7 +380,6 @@ const struct mips_opcode micromips_opcodes[] =
{"c.ngt.ps", "S,T", 0x54000bfc, 0xfc00ffff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
{"c.ngt.ps", "M,S,T", 0x54000bfc, 0xfc001fff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
{"cache", "k,~(b)", 0x20006000, 0xfc00f000, RD_b, 0, I1 },
-{"cache", "k,o(b)", 0, (int) M_CACHE_OB, INSN_MACRO, 0, I1 },
{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I1 },
{"ceil.l.d", "T,S", 0x5400533b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
{"ceil.l.s", "T,S", 0x5400133b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
@@ -596,29 +592,23 @@ const struct mips_opcode micromips_opcodes[] =
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
/* The macro has to be first to handle o32 correctly. */
-{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
-{"ld", "t,o(b)", 0xdc000000, 0xfc000000, RD_b|WR_t, 0, I3 },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
+{"ld", "t,o(b)", 0xdc000000, 0xfc000000, RD_b|WR_t, 0, I3 },
{"ldc1", "T,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 },
{"ldc1", "E,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 },
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_b|WR_CC, 0, I1 },
-{"ldc2", "E,o(b)", 0, (int) M_LDC2_OB, INSN_MACRO, 0, I1 },
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I1 },
{"l.d", "T,o(b)", 0xbc000000, 0xfc000000, RD_b|WR_T|FP_D, 0, I1 }, /* ldc1 */
{"l.d", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_t|RD_b, 0, I3 },
-{"ldl", "t,o(b)", 0, (int) M_LDL_OB, INSN_MACRO, 0, I3 },
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
{"ldm", "n,~(b)", 0x20007000, 0xfc00f000, RD_b, 0, I3 },
-{"ldm", "n,o(b)", 0, (int) M_LDM_OB, INSN_MACRO, 0, I3 },
{"ldm", "n,A(b)", 0, (int) M_LDM_AB, INSN_MACRO, 0, I3 },
{"ldp", "t,~(b)", 0x20004000, 0xfc00f000, RD_b|WR_t, 0, I3 },
-{"ldp", "t,o(b)", 0, (int) M_LDP_OB, INSN_MACRO, 0, I3 },
{"ldp", "t,A(b)", 0, (int) M_LDP_AB, INSN_MACRO, 0, I3 },
{"ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_t|RD_b, 0, I3 },
-{"ldr", "t,o(b)", 0, (int) M_LDR_OB, INSN_MACRO, 0, I3 },
{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
{"ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_D|RD_t|RD_b|FP_D, 0, I1 },
{"lh", "t,o(b)", 0x3c000000, 0xfc000000, RD_b|WR_t, 0, I1 },
@@ -632,10 +622,8 @@ const struct mips_opcode micromips_opcodes[] =
{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1 },
{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1 },
{"ll", "t,~(b)", 0x60003000, 0xfc00f000, RD_b|WR_t, 0, I1 },
-{"ll", "t,o(b)", 0, (int) M_LL_OB, INSN_MACRO, 0, I1 },
{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I1 },
{"lld", "t,~(b)", 0x60007000, 0xfc00f000, RD_b|WR_t, 0, I3 },
-{"lld", "t,o(b)", 0, (int) M_LLD_OB, INSN_MACRO, 0, I3 },
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 },
{"lui", "s,u", 0x41a00000, 0xffe00000, WR_s, 0, I1 },
{"luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_D|RD_t|RD_b|FP_D, 0, I1 },
@@ -649,32 +637,24 @@ const struct mips_opcode micromips_opcodes[] =
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_b|WR_CC, 0, I1 },
-{"lwc2", "E,o(b)", 0, (int) M_LWC2_OB, INSN_MACRO, 0, I1 },
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
{"l.s", "T,o(b)", 0x9c000000, 0xfc000000, RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"lwl", "t,~(b)", 0x60000000, 0xfc00f000, RD_b|WR_t, 0, I1 },
-{"lwl", "t,o(b)", 0, (int) M_LWL_OB, INSN_MACRO, 0, I1 },
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
{"lcache", "t,~(b)", 0x60000000, 0xfc00f000, RD_b|WR_t, 0, I1 }, /* same */
-{"lcache", "t,o(b)", 0, (int) M_LWL_OB, INSN_MACRO, 0, I1 },
{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
{"lwm", "mN,mJ(ms)", 0x4500, 0xffc0, NODS, RD_sp, I1 },
{"lwm", "n,~(b)", 0x20005000, 0xfc00f000, RD_b|NODS, 0, I1 },
-{"lwm", "n,o(b)", 0, (int) M_LWM_OB, INSN_MACRO, 0, I1 },
{"lwm", "n,A(b)", 0, (int) M_LWM_AB, INSN_MACRO, 0, I1 },
{"lwp", "t,~(b)", 0x20001000, 0xfc00f000, RD_b|WR_t|NODS, 0, I1 },
-{"lwp", "t,o(b)", 0, (int) M_LWP_OB, INSN_MACRO, 0, I1 },
{"lwp", "t,A(b)", 0, (int) M_LWP_AB, INSN_MACRO, 0, I1 },
{"lwr", "t,~(b)", 0x60001000, 0xfc00f000, RD_b|WR_t, 0, I1 },
-{"lwr", "t,o(b)", 0, (int) M_LWR_OB, INSN_MACRO, 0, I1 },
{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
{"lwu", "t,~(b)", 0x6000e000, 0xfc00f000, RD_b|WR_t, 0, I3 },
-{"lwu", "t,o(b)", 0, (int) M_LWU_OB, INSN_MACRO, 0, I3 },
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },
{"lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_D|RD_t|RD_b|FP_S, 0, I1 },
{"flush", "t,~(b)", 0x60001000, 0xfc00f000, RD_b|WR_t, 0, I1 }, /* same */
-{"flush", "t,o(b)", 0, (int) M_LWR_OB, INSN_MACRO, 0, I1 },
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
{"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, RD_b|RD_t|WR_d, 0, I1 },
{"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I1 },
@@ -819,15 +799,12 @@ const struct mips_opcode micromips_opcodes[] =
{"sb", "t,o(b)", 0x18000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
{"sc", "t,~(b)", 0x6000b000, 0xfc00f000, SM|RD_t|WR_t|RD_b, 0, I1 },
-{"sc", "t,o(b)", 0, (int) M_SC_OB, INSN_MACRO, 0, I1 },
{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I1 },
{"scd", "t,~(b)", 0x6000f000, 0xfc00f000, SM|RD_t|WR_t|RD_b, 0, I3 },
-{"scd", "t,o(b)", 0, (int) M_SCD_OB, INSN_MACRO, 0, I3 },
{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 },
/* The macro has to be first to handle o32 correctly. */
-{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
-{"sd", "t,o(b)", 0xd8000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
+{"sd", "t,o(b)", 0xd8000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sdbbp", "", 0x46c0, 0xffff, TRAP, 0, I1 },
{"sdbbp", "", 0x0000db7c, 0xffffffff, TRAP, 0, I1 },
{"sdbbp", "mO", 0x46c0, 0xfff0, TRAP, 0, I1 },
@@ -837,21 +814,16 @@ const struct mips_opcode micromips_opcodes[] =
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"sdc2", "E,~(b)", 0x2000a000, 0xfc00f000, SM|RD_C2|RD_b, 0, I1 },
-{"sdc2", "E,o(b)", 0, (int) M_SDC2_OB, INSN_MACRO, 0, I1 },
{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I1 },
{"s.d", "T,o(b)", 0xb8000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I1 }, /* sdc1 */
{"s.d", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"sdl", "t,~(b)", 0x6000c000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
-{"sdl", "t,o(b)", 0, (int) M_SDL_OB, INSN_MACRO, 0, I3 },
{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
{"sdm", "n,~(b)", 0x2000f000, 0xfc00f000, SM|RD_b, 0, I3 },
-{"sdm", "n,o(b)", 0, (int) M_SDM_OB, INSN_MACRO, 0, I3 },
{"sdm", "n,A(b)", 0, (int) M_SDM_AB, INSN_MACRO, 0, I3 },
{"sdp", "t,~(b)", 0x2000c000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
-{"sdp", "t,o(b)", 0, (int) M_SDP_OB, INSN_MACRO, 0, I3 },
{"sdp", "t,A(b)", 0, (int) M_SDP_AB, INSN_MACRO, 0, I3 },
{"sdr", "t,~(b)", 0x6000d000, 0xfc00f000, SM|RD_t|RD_b, 0, I3 },
-{"sdr", "t,o(b)", 0, (int) M_SDR_OB, INSN_MACRO, 0, I3 },
{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 },
{"sdxc1", "D,t(b)", 0x54000108, 0xfc0007ff, SM|RD_t|RD_b|FP_D, RD_D, I1 },
{"seb", "t,r", 0x00002b3c, 0xfc00ffff, WR_t|RD_s, 0, I1 },
@@ -913,28 +885,21 @@ const struct mips_opcode micromips_opcodes[] =
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"swc2", "E,~(b)", 0x20008000, 0xfc00f000, SM|RD_C2|RD_b, 0, I1 },
-{"swc2", "E,o(b)", 0, (int) M_SWC2_OB, INSN_MACRO, 0, I1 },
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
{"s.s", "T,o(b)", 0x98000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"swl", "t,~(b)", 0x60008000, 0xfc00f000, SM|RD_t|RD_b, 0, I1 },
-{"swl", "t,o(b)", 0, (int) M_SWL_OB, INSN_MACRO, 0, I1 },
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
{"scache", "t,~(b)", 0x60008000, 0xfc00f000, SM|RD_t|RD_b, 0, I1 }, /* same */
-{"scache", "t,o(b)", 0, (int) M_SWL_OB, INSN_MACRO, 0, I1 },
{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
{"swm", "mN,mJ(ms)", 0x4540, 0xffc0, NODS, RD_sp, I1 },
{"swm", "n,~(b)", 0x2000d000, 0xfc00f000, SM|RD_b|NODS, 0, I1 },
-{"swm", "n,o(b)", 0, (int) M_SWM_OB, INSN_MACRO, 0, I1 },
{"swm", "n,A(b)", 0, (int) M_SWM_AB, INSN_MACRO, 0, I1 },
{"swp", "t,~(b)", 0x20009000, 0xfc00f000, SM|RD_t|RD_b|NODS, 0, I1 },
-{"swp", "t,o(b)", 0, (int) M_SWP_OB, INSN_MACRO, 0, I1 },
{"swp", "t,A(b)", 0, (int) M_SWP_AB, INSN_MACRO, 0, I1 },
{"swr", "t,~(b)", 0x60009000, 0xfc00f000, SM|RD_b|RD_t, 0, I1 },
-{"swr", "t,o(b)", 0, (int) M_SWR_OB, INSN_MACRO, 0, I1 },
{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
{"invalidate", "t,~(b)",0x60009000, 0xfc00f000, SM|RD_b|RD_t, 0, I1 }, /* same */
-{"invalidate", "t,o(b)",0, (int) M_SWR_OB, INSN_MACRO, 0, I1 },
{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
{"swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, SM|RD_t|RD_b|FP_S, RD_D, I1 },
{"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, 0, I1 },
@@ -993,20 +958,13 @@ const struct mips_opcode micromips_opcodes[] =
{"trunc.l.s", "T,S", 0x5400233b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
{"trunc.w.d", "T,S", 0x54006b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
{"trunc.w.s", "T,S", 0x54002b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
-{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 },
-{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 },
-{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 },
-{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
-{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
-{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
-{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
-{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
-{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I1 },
-{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I1 },
-{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
-{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
-{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
-{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
+{"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3 },
+{"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1 },
+{"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1 },
+{"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1 },
+{"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I1 },
+{"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1 },
+{"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1 },
{"wait", "", 0x0000937c, 0xffffffff, NODS, 0, I1 },
{"wait", "B", 0x0000937c, 0xfc00ffff, NODS, 0, I1 },
{"wrpgpr", "t,r", 0x0000f17c, 0xfc00ffff, RD_s, 0, I1 },
@@ -1018,52 +976,36 @@ const struct mips_opcode micromips_opcodes[] =
{"xori", "t,r,i", 0x70000000, 0xfc000000, WR_t|RD_s, 0, I1 },
/* microMIPS Enhanced VA Scheme */
{"lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
-{"lbue", "t,o(b)", 0, (int) M_LBUE_OB, INSN_MACRO, 0, 0, EVA },
{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA },
{"lhue", "t,+j(b)", 0x60006200, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
-{"lhue", "t,o(b)", 0, (int) M_LHUE_OB, INSN_MACRO, 0, 0, EVA },
{"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA },
{"lbe", "t,+j(b)", 0x60006800, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
-{"lbe", "t,o(b)", 0, (int) M_LBE_OB, INSN_MACRO, 0, 0, EVA },
{"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA },
{"lhe", "t,+j(b)", 0x60006a00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
-{"lhe", "t,o(b)", 0, (int) M_LHE_OB, INSN_MACRO, 0, 0, EVA },
{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA },
{"lle", "t,+j(b)", 0x60006c00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
-{"lle", "t,o(b)", 0, (int) M_LLE_OB, INSN_MACRO, 0, 0, EVA },
{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA },
{"lwe", "t,+j(b)", 0x60006e00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
-{"lwe", "t,o(b)", 0, (int) M_LWE_OB, INSN_MACRO, 0, 0, EVA },
{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA },
{"lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
-{"lwle", "t,o(b)", 0, (int) M_LWLE_OB, INSN_MACRO, 0, 0, EVA },
{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA },
{"lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA },
-{"lwre", "t,o(b)", 0, (int) M_LWRE_OB, INSN_MACRO, 0, 0, EVA },
{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA },
{"sbe", "t,+j(b)", 0x6000a800, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
-{"sbe", "t,o(b)", 0, (int) M_SBE_OB, INSN_MACRO, 0, 0, EVA },
{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA },
{"sce", "t,+j(b)", 0x6000ac00, 0xfc00fe00, SM|RD_t|WR_t|RD_b, 0, 0, EVA },
-{"sce", "t,o(b)", 0, (int) M_SCE_OB, INSN_MACRO, 0, 0, EVA },
{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA },
{"she", "t,+j(b)", 0x6000aa00, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
-{"she", "t,o(b)", 0, (int) M_SHE_OB, INSN_MACRO, 0, 0, EVA },
{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA },
{"swe", "t,+j(b)", 0x6000ae00, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
-{"swe", "t,o(b)", 0, (int) M_SWE_OB, INSN_MACRO, 0, 0, EVA },
{"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA },
{"swle", "t,+j(b)", 0x6000a000, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
-{"swle", "t,o(b)", 0, (int) M_SWLE_OB, INSN_MACRO, 0, 0, EVA },
{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA },
{"swre", "t,+j(b)", 0x6000a200, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA },
-{"swre", "t,o(b)", 0, (int) M_SWRE_OB, INSN_MACRO, 0, 0, EVA },
{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA },
{"cachee", "k,+j(b)", 0x6000a600, 0xfc00fe00, RD_b, 0, 0, EVA },
-{"cachee", "k,o(b)", 0, (int) M_CACHEE_OB,INSN_MACRO, 0, 0, EVA },
{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA },
{"prefe", "k,+j(b)", 0x6000a400, 0xfc00fe00, RD_b, 0, 0, EVA },
-{"prefe", "k,o(b)", 0, (int) M_PREFE_OB, INSN_MACRO, 0, 0, EVA },
{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA },
/* MIPS DSP ASE. */
{"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 },
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index e33b561006..9a80de6428 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -300,7 +300,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F },
{"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E },
{"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, SM|RD_b|NODS, 0, 0, MC },
-{"aclr", "\\,o(b)", 0, (int) M_ACLR_OB, INSN_MACRO, 0, 0, MC },
{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC },
{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
@@ -340,7 +339,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX },
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, SM|RD_b|NODS, 0, 0, MC },
-{"aset", "\\,o(b)", 0, (int) M_ASET_OB, INSN_MACRO, 0, 0, MC },
{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC },
{"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
/* b is at the top of the table. */
@@ -869,9 +867,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"lwux", "d,t(b)", 0x7c00040a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2 },
{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
/* The macro has to be first to handle o32 correctly. */
-{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
-{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
+{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
@@ -880,7 +877,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2, 0, SF }, /* ldc1 */
-{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
@@ -1397,10 +1393,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, SB1, MX },
{"rzu.ob", "D,Q", 0x48000020, 0xfc20f83f, WR_D|RD_S|RD_T, 0, N54 },
{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, 0, MX },
-{"saa", "t,o(b)", 0, (int) M_SAA_OB, INSN_MACRO, 0, IOCTP },
{"saa", "t,A(b)", 0, (int) M_SAA_AB, INSN_MACRO, 0, IOCTP },
{"saa", "t,(b)", 0x70000018, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP },
-{"saad", "t,o(b)", 0, (int) M_SAAD_OB, INSN_MACRO, 0, IOCTP },
{"saad", "t,A(b)", 0, (int) M_SAAD_AB, INSN_MACRO, 0, IOCTP },
{"saad", "t,(b)", 0x70000019, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP },
{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
@@ -1410,9 +1404,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3, 0, EE },
{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, EE },
/* The macro has to be first to handle o32 correctly. */
-{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
-{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
+{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 },
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 },
{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 },
@@ -1427,7 +1420,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE },
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2, 0, SF },
-{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
@@ -1636,20 +1628,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, 0, EE },
{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, 0, EE },
{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, INSN2_M_FP_S, I1, 0, EE },
-{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 },
-{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 },
-{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 },
-{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
-{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
-{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
-{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
-{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
-{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 },
-{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 },
-{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
-{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
-{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
-{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
+{"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3 },
+{"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1 },
+{"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1 },
+{"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1 },
+{"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I3 },
+{"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1 },
+{"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1 },
{"v3mulu", "d,v,t", 0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
{"vmm0", "d,v,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
{"vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
@@ -2258,52 +2243,36 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
/* MIPS Enhanced VA Scheme */
{"lbue", "t,+j(b)", 0x7c000028, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
-{"lbue", "t,o(b)", 0, (int) M_LBUE_OB, INSN_MACRO, 0, 0, EVA },
{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA },
{"lhue", "t,+j(b)", 0x7c000029, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
-{"lhue", "t,o(b)", 0, (int) M_LHUE_OB, INSN_MACRO, 0, 0, EVA },
{"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA },
{"lbe", "t,+j(b)", 0x7c00002c, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
-{"lbe", "t,o(b)", 0, (int) M_LBE_OB, INSN_MACRO, 0, 0, EVA },
{"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA },
{"lhe", "t,+j(b)", 0x7c00002d, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
-{"lhe", "t,o(b)", 0, (int) M_LHE_OB, INSN_MACRO, 0, 0, EVA },
{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA },
{"lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
-{"lle", "t,o(b)", 0, (int) M_LLE_OB, INSN_MACRO, 0, 0, EVA },
{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA },
{"lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
-{"lwe", "t,o(b)", 0, (int) M_LWE_OB, INSN_MACRO, 0, 0, EVA },
{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA },
{"lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
-{"lwle", "t,o(b)", 0, (int) M_LWLE_OB, INSN_MACRO, 0, 0, EVA },
{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA },
{"lwre", "t,+j(b)", 0x7c00001a, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA },
-{"lwre", "t,o(b)", 0, (int) M_LWRE_OB, INSN_MACRO, 0, 0, EVA },
{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA },
{"sbe", "t,+j(b)", 0x7c00001c, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
-{"sbe", "t,o(b)", 0, (int) M_SBE_OB, INSN_MACRO, 0, 0, EVA },
{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA },
{"sce", "t,+j(b)", 0x7c00001e, 0xfc00007f, SM|RD_t|WR_t|RD_b, 0, 0, EVA },
-{"sce", "t,o(b)", 0, (int) M_SCE_OB, INSN_MACRO, 0, 0, EVA },
{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA },
{"she", "t,+j(b)", 0x7c00001d, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
-{"she", "t,o(b)", 0, (int) M_SHE_OB, INSN_MACRO, 0, 0, EVA },
{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA },
{"swe", "t,+j(b)", 0x7c00001f, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
-{"swe", "t,o(b)", 0, (int) M_SWE_OB, INSN_MACRO, 0, 0, EVA },
{"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA },
{"swle", "t,+j(b)", 0x7c000021, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
-{"swle", "t,o(b)", 0, (int) M_SWLE_OB, INSN_MACRO, 0, 0, EVA },
{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA },
{"swre", "t,+j(b)", 0x7c000022, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA },
-{"swre", "t,o(b)", 0, (int) M_SWRE_OB, INSN_MACRO, 0, 0, EVA },
{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA },
{"cachee", "k,+j(b)", 0x7c00001b, 0xfc00007f, RD_b, 0, 0, EVA },
-{"cachee", "k,o(b)", 0, (int) M_CACHEE_OB,INSN_MACRO, 0, 0, EVA },
{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA },
{"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_b, 0, 0, EVA },
-{"prefe", "k,o(b)", 0, (int) M_PREFE_OB, INSN_MACRO, 0, 0, EVA },
{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA },
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the