diff options
| -rw-r--r-- | gas/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/mips.exp | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/mips64.d | 17 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/mips64.s | 22 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 9 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 18 |
6 files changed, 68 insertions, 4 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 803d7fc2e3..94325958a2 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -32,6 +32,11 @@ to use their correct names. Add tests for break and sdbbp. * gas/mips/mips32.s: Likewise. + * gas/mips/mips64.s: Add test for assembly of MIPS64 + extensions. + * gas/mips/mips64.d: Likewise. + * gas/mips/mips.exp: Test using the new "mips64" test. + 2000-12-01 Chris Demetriou <cgd@sibyte.com> * gas/mips/mips16.d: Expect mips16 nops to be used for padding diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index a7deff8c90..b5deb356b9 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -89,6 +89,7 @@ if [istarget mips*-*-*] then { run_dump_test "lineno" run_dump_test "sync" run_dump_test "mips32" + run_dump_test "mips64" # Make sure that -mcpu=FOO and -mFOO are equivalent. Assemble a file # containing 4650-specific instructions with -m4650 and -mcpu=4650, diff --git a/gas/testsuite/gas/mips/mips64.d b/gas/testsuite/gas/mips/mips64.d new file mode 100644 index 0000000000..1baa367a19 --- /dev/null +++ b/gas/testsuite/gas/mips/mips64.d @@ -0,0 +1,17 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS MIPS64 instructions +#as: -mips64 + +# Check MIPS32 instruction assembly + +.*: +file format elf.*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 70410825 dclo \$at,\$v0 +0+0004 <[^>]*> 70831824 dclz \$v1,\$a0 +0+0008 <[^>]*> 48232000 dmfc2 \$v1,\$4 +0+000c <[^>]*> 48242800 dmfc2 \$a0,\$5 +0+0010 <[^>]*> 48253007 dmfc2 \$a1,\$6,7 +0+0014 <[^>]*> 48a63800 dmtc2 \$a2,\$7 +0+0018 <[^>]*> 48a74000 dmtc2 \$a3,\$8 +0+001c <[^>]*> 48a84807 dmtc2 \$t0,\$9,7 diff --git a/gas/testsuite/gas/mips/mips64.s b/gas/testsuite/gas/mips/mips64.s new file mode 100644 index 0000000000..bf5e6b74ef --- /dev/null +++ b/gas/testsuite/gas/mips/mips64.s @@ -0,0 +1,22 @@ +# source file to test assembly of mips64 instructions + + .set noreorder + .set noat + + .globl text_label .text +text_label: + + # unprivileged CPU instructions + + dclo $1, $2 + dclz $3, $4 + + # unprivileged coprocessor instructions. + # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes. + + dmfc2 $3, $4 + dmfc2 $4, $5, 0 # disassembles without sel + dmfc2 $5, $6, 7 + dmtc2 $6, $7 + dmtc2 $7, $8, 0 # disassembles without sel + dmtc2 $8, $9, 7 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4c8972f287..6ef3f54442 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -6,6 +6,15 @@ * mips-opc.c (M1, M2): Delete. (mips_builtin_opcodes): Remove all uses of M1. + * mips-opc.c (mips_builtin_opcodes): Make the dmfc2 and dmtc2 + instructions take "G" format second operands and use the + correct flags. + There are mfc3 and mtc3 opcodes, so add dmfc3 and dmtc3 opcodes to + match. + Delete "sel" code operands from mfc1 and mtc1. + Add MIPS64 opcode changes (dclo, dclz), and "sel" code variants + for dm[ft]c[023]. + 2000-12-03 Ed Satterthwaite ehs@sibyte.com and Chris Demetriou cgd@sibyte.com diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 81aaf33f27..e6b25cb9f1 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -359,6 +359,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 }, +{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, I64 }, +{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, I64 }, /* dctr and dctw are used on the r5000. */ {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 }, {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 }, @@ -394,11 +396,21 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, V1 }, {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 }, +{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 }, {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 }, +{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 }, {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, +{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, -{"dmfc2", "t,S", 0x48200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, -{"dmtc2", "t,S", 0x48a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, +{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, +{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, I3 }, +{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, I64 }, +{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I3 }, +{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I64 }, +{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, I3 }, +{"dmfc3", "t,G,H", 0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3, I64 }, +{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I3 }, +{"dmtc3", "t,G,H", 0x4ca00000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I64 }, {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 }, {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 }, {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 }, @@ -549,7 +561,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 }, {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, -{"mfc1", "t,G,H", 0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S, I32 }, {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 }, {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, @@ -587,7 +598,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 }, {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, -{"mtc1", "t,G,H", 0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S, I32 }, {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 }, {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 }, {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 }, |