diff options
| -rw-r--r-- | gas/testsuite/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/simd-intel.d | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/simd.d | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/simd.s | 1 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 2 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 4 |
7 files changed, 19 insertions, 3 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index e1e968998f..33eaba07c3 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2013-07-08 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/13572 + * gas/i386/simd.s: Add a test for cvttps2pi. + * gas/i386/simd-intel.d: Updated. + * gas/i386/simd.d: Likewise. + 2013-07-08 Richard Sandiford <rdsandiford@googlemail.com> * gas/mips/la.s, gas/mips/la.d, gas/mips/la-svr4pic.d, diff --git a/gas/testsuite/gas/i386/simd-intel.d b/gas/testsuite/gas/i386/simd-intel.d index c5ff4b4042..5b72fd7ad4 100644 --- a/gas/testsuite/gas/i386/simd-intel.d +++ b/gas/testsuite/gas/i386/simd-intel.d @@ -196,4 +196,5 @@ Disassembly of section .text: [ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sd xmm1,DWORD PTR \[eax\] [ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ss xmm1,DWORD PTR \[eax\] [ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sd xmm1,DWORD PTR \[eax\] +[ ]*[a-f0-9]+: 0f 2c 00 cvttps2pi mm0,QWORD PTR \[eax\] #pass diff --git a/gas/testsuite/gas/i386/simd.d b/gas/testsuite/gas/i386/simd.d index 6410d79a56..2567612389 100644 --- a/gas/testsuite/gas/i386/simd.d +++ b/gas/testsuite/gas/i386/simd.d @@ -195,4 +195,5 @@ Disassembly of section .text: [ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sdl \(%eax\),%xmm1 [ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ssl \(%eax\),%xmm1 [ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sdl \(%eax\),%xmm1 +[ ]*[a-f0-9]+: 0f 2c 00 cvttps2pi \(%eax\),%mm0 #pass diff --git a/gas/testsuite/gas/i386/simd.s b/gas/testsuite/gas/i386/simd.s index 633cf2fef5..faa37cfe88 100644 --- a/gas/testsuite/gas/i386/simd.s +++ b/gas/testsuite/gas/i386/simd.s @@ -196,3 +196,4 @@ cvtsi2sd xmm1,DWORD PTR [eax] cvtsi2sd xmm1,[eax] cvtsi2ssd xmm1,DWORD PTR [eax] cvtsi2sdd xmm1,DWORD PTR [eax] +cvttps2pi mm0,QWORD PTR[eax] diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 88dd9728fb..905b37e1e3 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2013-07-08 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/13572 + * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi. + * i386-tbl.h: Regenerated. + 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 63962939dc..b1f438f327 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1198,7 +1198,7 @@ cvtsi2ss, 2, 0xf30f2a, None, 2, CpuSSE|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf cvtsi2ss, 2, 0xf30f2a, None, 2, CpuSSE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } cvtss2si, 2, 0xf32d, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } cvtss2si, 2, 0xf30f2d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } -cvttps2pi, 2, 0xf2c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } +cvttps2pi, 2, 0xf2c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } cvttss2si, 2, 0xf32c, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } cvttss2si, 2, 0xf30f2c, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } divps, 2, 0x5e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 114d101f1d..187fafb639 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -11972,8 +11972,8 @@ const insn_template i386_optab[] = 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 0 } }, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, |