diff options
| -rw-r--r-- | gas/testsuite/ChangeLog | 9 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/i386.exp | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/prefetch-intel.d | 27 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/prefetch.d | 26 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/prefetch.s | 18 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64-prefetch-intel.d | 27 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64-prefetch.d | 27 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 9 | ||||
| -rw-r--r-- | opcodes/i386-dis.c | 30 |
9 files changed, 177 insertions, 0 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 56a01d8fd3..57b39a39fe 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2012-08-07 Roland McGrath <mcgrathr@google.com> + + * gas/i386/prefetch.s: New file. + * gas/i386/prefetch.d: New file. + * gas/i386/prefetch-intel.d: New file. + * gas/i386/x86-64-prefetch.d: New file. + * gas/i386/x86-64-prefetch-intel.d: New file. + * gas/i386/i386.exp: Run them. + 2012-08-07 Jan Beulich <jbeulich@suse.com> * gas/i386/x86-64-segovr.{s,l}: New. diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 82cef63ab9..7b93babb67 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -216,6 +216,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "adx-intel" run_dump_test "rdseed" run_dump_test "rdseed-intel" + run_dump_test "prefetch" + run_dump_test "prefetch-intel" # These tests require support for 8 and 16 bit relocs, # so we only run them for ELF and COFF targets. @@ -457,6 +459,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-adx-intel" run_dump_test "x86-64-rdseed" run_dump_test "x86-64-rdseed-intel" + run_dump_test "x86-64-prefetch" + run_dump_test "x86-64-prefetch-intel" if { ![istarget "*-*-aix*"] && ![istarget "*-*-beos*"] diff --git a/gas/testsuite/gas/i386/prefetch-intel.d b/gas/testsuite/gas/i386/prefetch-intel.d new file mode 100644 index 0000000000..fbdd2ef4fe --- /dev/null +++ b/gas/testsuite/gas/i386/prefetch-intel.d @@ -0,0 +1,27 @@ +#objdump: -dw -Mintel +#name: i386 prefetch (Intel disassembly) +#source: prefetch.s + +.*: +file format .* + +Disassembly of section .text: + +0+ <amd_prefetch>: +\s*[a-f0-9]+: 0f 0d 00 prefetch BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 0d 08 prefetchw BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 0d 10 prefetch BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 0d 18 prefetch BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 0d 20 prefetch BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 0d 28 prefetch BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 0d 30 prefetch BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 0d 38 prefetch BYTE PTR \[eax\] + +0+[0-9a-f]+ <intel_prefetch>: +\s*[a-f0-9]+: 0f 18 00 prefetchnta BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 18 08 prefetcht0 BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 18 10 prefetcht1 BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 18 18 prefetcht2 BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 18 20 nop/reserved BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 18 28 nop/reserved BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 18 30 nop/reserved BYTE PTR \[eax\] +\s*[a-f0-9]+: 0f 18 38 nop/reserved BYTE PTR \[eax\] diff --git a/gas/testsuite/gas/i386/prefetch.d b/gas/testsuite/gas/i386/prefetch.d new file mode 100644 index 0000000000..13980bc257 --- /dev/null +++ b/gas/testsuite/gas/i386/prefetch.d @@ -0,0 +1,26 @@ +#objdump: -dw +#name: i386 prefetch + +.*: +file format .* + +Disassembly of section .text: + +0+ <amd_prefetch>: +\s*[a-f0-9]+: 0f 0d 00 prefetch \(%eax\) +\s*[a-f0-9]+: 0f 0d 08 prefetchw \(%eax\) +\s*[a-f0-9]+: 0f 0d 10 prefetch \(%eax\) +\s*[a-f0-9]+: 0f 0d 18 prefetch \(%eax\) +\s*[a-f0-9]+: 0f 0d 20 prefetch \(%eax\) +\s*[a-f0-9]+: 0f 0d 28 prefetch \(%eax\) +\s*[a-f0-9]+: 0f 0d 30 prefetch \(%eax\) +\s*[a-f0-9]+: 0f 0d 38 prefetch \(%eax\) + +0+[0-9a-f]+ <intel_prefetch>: +\s*[a-f0-9]+: 0f 18 00 prefetchnta \(%eax\) +\s*[a-f0-9]+: 0f 18 08 prefetcht0 \(%eax\) +\s*[a-f0-9]+: 0f 18 10 prefetcht1 \(%eax\) +\s*[a-f0-9]+: 0f 18 18 prefetcht2 \(%eax\) +\s*[a-f0-9]+: 0f 18 20 nop/reserved \(%eax\) +\s*[a-f0-9]+: 0f 18 28 nop/reserved \(%eax\) +\s*[a-f0-9]+: 0f 18 30 nop/reserved \(%eax\) +\s*[a-f0-9]+: 0f 18 38 nop/reserved \(%eax\) diff --git a/gas/testsuite/gas/i386/prefetch.s b/gas/testsuite/gas/i386/prefetch.s new file mode 100644 index 0000000000..c0f92ae2a0 --- /dev/null +++ b/gas/testsuite/gas/i386/prefetch.s @@ -0,0 +1,18 @@ +.macro try opcode:vararg + .byte \opcode, 0x00 + .byte \opcode, 0x08 + .byte \opcode, 0x10 + .byte \opcode, 0x18 + .byte \opcode, 0x20 + .byte \opcode, 0x28 + .byte \opcode, 0x30 + .byte \opcode, 0x38 +.endm + +.text + +amd_prefetch: + try 0x0f, 0x0d + +intel_prefetch: + try 0x0f, 0x18 diff --git a/gas/testsuite/gas/i386/x86-64-prefetch-intel.d b/gas/testsuite/gas/i386/x86-64-prefetch-intel.d new file mode 100644 index 0000000000..9941946210 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-prefetch-intel.d @@ -0,0 +1,27 @@ +#objdump: -dw -Mintel +#name: x86-64 prefetch (Intel disassembly) +#source: prefetch.s + +.*: +file format .* + +Disassembly of section .text: + +0+ <amd_prefetch>: +\s*[a-f0-9]+: 0f 0d 00 prefetch BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 0d 08 prefetchw BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 0d 10 prefetch BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 0d 18 prefetch BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 0d 20 prefetch BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 0d 28 prefetch BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 0d 30 prefetch BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 0d 38 prefetch BYTE PTR \[rax\] + +0+[0-9a-f]+ <intel_prefetch>: +\s*[a-f0-9]+: 0f 18 00 prefetchnta BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 18 08 prefetcht0 BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 18 10 prefetcht1 BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 18 18 prefetcht2 BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 18 20 nop/reserved BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 18 28 nop/reserved BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 18 30 nop/reserved BYTE PTR \[rax\] +\s*[a-f0-9]+: 0f 18 38 nop/reserved BYTE PTR \[rax\] diff --git a/gas/testsuite/gas/i386/x86-64-prefetch.d b/gas/testsuite/gas/i386/x86-64-prefetch.d new file mode 100644 index 0000000000..476d9f20cb --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-prefetch.d @@ -0,0 +1,27 @@ +#objdump: -dw +#name: x86-64 prefetch +#source: prefetch.s + +.*: +file format .* + +Disassembly of section .text: + +0+ <amd_prefetch>: +\s*[a-f0-9]+: 0f 0d 00 prefetch \(%rax\) +\s*[a-f0-9]+: 0f 0d 08 prefetchw \(%rax\) +\s*[a-f0-9]+: 0f 0d 10 prefetch \(%rax\) +\s*[a-f0-9]+: 0f 0d 18 prefetch \(%rax\) +\s*[a-f0-9]+: 0f 0d 20 prefetch \(%rax\) +\s*[a-f0-9]+: 0f 0d 28 prefetch \(%rax\) +\s*[a-f0-9]+: 0f 0d 30 prefetch \(%rax\) +\s*[a-f0-9]+: 0f 0d 38 prefetch \(%rax\) + +0+[0-9a-f]+ <intel_prefetch>: +\s*[a-f0-9]+: 0f 18 00 prefetchnta \(%rax\) +\s*[a-f0-9]+: 0f 18 08 prefetcht0 \(%rax\) +\s*[a-f0-9]+: 0f 18 10 prefetcht1 \(%rax\) +\s*[a-f0-9]+: 0f 18 18 prefetcht2 \(%rax\) +\s*[a-f0-9]+: 0f 18 20 nop/reserved \(%rax\) +\s*[a-f0-9]+: 0f 18 28 nop/reserved \(%rax\) +\s*[a-f0-9]+: 0f 18 30 nop/reserved \(%rax\) +\s*[a-f0-9]+: 0f 18 38 nop/reserved \(%rax\) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 77063ce7c6..0b55bb8040 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,12 @@ +2012-08-07 Roland McGrath <mcgrathr@google.com> + + * i386-dis.c (reg_table): Fill out REG_0F0D table with + AMD-reserved cases as "prefetch". + (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants. + (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise. + (reg_table): Use those under REG_0F18. + (mod_table): Add those cases as "nop/reserved". + 2012-08-07 Jan Beulich <jbeulich@suse.com> * i386-opc.tbl: Remove "FIXME" comments from SVME instructions. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index da5ede57d2..15c968a529 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -668,6 +668,10 @@ enum MOD_0F18_REG_1, MOD_0F18_REG_2, MOD_0F18_REG_3, + MOD_0F18_REG_4, + MOD_0F18_REG_5, + MOD_0F18_REG_6, + MOD_0F18_REG_7, MOD_0F20, MOD_0F21, MOD_0F22, @@ -2652,6 +2656,12 @@ static const struct dis386 reg_table[][8] = { { { "prefetch", { Mb } }, { "prefetchw", { Mb } }, + { "prefetch", { Mb } }, + { "prefetch", { Mb } }, + { "prefetch", { Mb } }, + { "prefetch", { Mb } }, + { "prefetch", { Mb } }, + { "prefetch", { Mb } }, }, /* REG_0F18 */ { @@ -2659,6 +2669,10 @@ static const struct dis386 reg_table[][8] = { { MOD_TABLE (MOD_0F18_REG_1) }, { MOD_TABLE (MOD_0F18_REG_2) }, { MOD_TABLE (MOD_0F18_REG_3) }, + { MOD_TABLE (MOD_0F18_REG_4) }, + { MOD_TABLE (MOD_0F18_REG_5) }, + { MOD_TABLE (MOD_0F18_REG_6) }, + { MOD_TABLE (MOD_0F18_REG_7) }, }, /* REG_0F71 */ { @@ -10221,6 +10235,22 @@ static const struct dis386 mod_table[][2] = { { "prefetcht2", { Mb } }, }, { + /* MOD_0F18_REG_4 */ + { "nop/reserved", { Mb } }, + }, + { + /* MOD_0F18_REG_5 */ + { "nop/reserved", { Mb } }, + }, + { + /* MOD_0F18_REG_6 */ + { "nop/reserved", { Mb } }, + }, + { + /* MOD_0F18_REG_7 */ + { "nop/reserved", { Mb } }, + }, + { /* MOD_0F20 */ { Bad_Opcode }, { "movZ", { Rm, Cm } }, |