diff options
| -rw-r--r-- | gas/ChangeLog | 8 | ||||
| -rw-r--r-- | gas/config/tc-m68k.c | 374 |
2 files changed, 199 insertions, 183 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 934d674868..365fcadb59 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +2003-10-17 Paul Dale <pauli@snapgear.com> + Bernardo Innocenti <bernie@develer.com> + + * config/tc-m68k.c (make_pcrel_absolute): Enforce + PC-relative jumps with --pcrel. + (md_convert_frag_1): Likewise. + (md_create_long_jump): Likewise. + 2003-10-17 Shrinivas Atre <shrinivasa@KPITCummins.com> * config/tc-h8300.c (PSIZE): Correct for Normal mode. diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c index 2c213c6a15..5539ed126d 100644 --- a/gas/config/tc-m68k.c +++ b/gas/config/tc-m68k.c @@ -55,7 +55,7 @@ const char line_comment_chars[] = "#*"; const char line_separator_chars[] = ";"; -/* Chars that can be used to separate mant from exp in floating point nums */ +/* Chars that can be used to separate mant from exp in floating point nums. */ const char EXP_CHARS[] = "eE"; /* Chars that mean this number is a floating point constant, as @@ -67,7 +67,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; changed in read.c . Ideally it shouldn't have to know about it at all, but nothing is ideal around here. */ -const int md_reloc_size = 8; /* Size of relocation record */ +const int md_reloc_size = 8; /* Size of relocation record. */ /* Are we trying to generate PIC code? If so, absolute references ought to be made into linkage table references or pc-relative @@ -75,8 +75,8 @@ const int md_reloc_size = 8; /* Size of relocation record */ to denote pic relocations. */ int flag_want_pic; -static int flag_short_refs; /* -l option */ -static int flag_long_jumps; /* -S option */ +static int flag_short_refs; /* -l option. */ +static int flag_long_jumps; /* -S option. */ static int flag_keep_pcrel; /* --pcrel option. */ #ifdef REGISTER_PREFIX_OPTIONAL @@ -114,7 +114,6 @@ static enum m68k_size m68k_index_width_default = SIZE_LONG; /* We want to warn if any text labels are misaligned. In order to get the right line number, we need to record the line number for each label. */ - struct label_line { struct label_line *next; @@ -132,8 +131,8 @@ static struct label_line *labels; static struct label_line *current_label; -/* Its an arbitrary name: This means I don't approve of it */ -/* See flames below */ +/* Its an arbitrary name: This means I don't approve of it. + See flames below. */ static struct obstack robyn; struct m68k_incant @@ -177,32 +176,32 @@ static const enum m68k_register mcf_control_regs[] = { static const enum m68k_register *control_regs; -/* internal form of a 68020 instruction */ +/* Internal form of a 68020 instruction. */ struct m68k_it { const char *error; - const char *args; /* list of opcode info */ + const char *args; /* List of opcode info. */ int numargs; - int numo; /* Number of shorts in opcode */ + int numo; /* Number of shorts in opcode. */ short opcode[11]; struct m68k_op operands[6]; - int nexp; /* number of exprs in use */ + int nexp; /* Number of exprs in use. */ struct m68k_exp exprs[4]; - int nfrag; /* Number of frags we have to produce */ + int nfrag; /* Number of frags we have to produce. */ struct { - int fragoff; /* Where in the current opcode the frag ends */ + int fragoff; /* Where in the current opcode the frag ends. */ symbolS *fadd; offsetT foff; int fragty; } fragb[4]; - int nrel; /* Num of reloc strucs in use */ + int nrel; /* Num of reloc strucs in use. */ struct { int n; @@ -223,7 +222,7 @@ struct m68k_it enum pic_relocation pic_reloc; #endif } - reloc[5]; /* Five is enough??? */ + reloc[5]; /* Five is enough??? */ }; #define cpu_of_arch(x) ((x) & (m68000up|mcf)) @@ -231,27 +230,26 @@ struct m68k_it #define mmu_of_arch(x) ((x) & mmmu) #define arch_coldfire_p(x) (((x) & mcf) != 0) -/* Macros for determining if cpu supports a specific addressing mode */ +/* Macros for determining if cpu supports a specific addressing mode. */ #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407)) -static struct m68k_it the_ins; /* the instruction being assembled */ +static struct m68k_it the_ins; /* The instruction being assembled. */ #define op(ex) ((ex)->exp.X_op) #define adds(ex) ((ex)->exp.X_add_symbol) #define subs(ex) ((ex)->exp.X_op_symbol) #define offs(ex) ((ex)->exp.X_add_number) -/* Macros for adding things to the m68k_it struct */ - +/* Macros for adding things to the m68k_it struct. */ #define addword(w) the_ins.opcode[the_ins.numo++]=(w) /* Static functions. */ - static void insop PARAMS ((int, const struct m68k_incant *)); static void add_fix PARAMS ((int, struct m68k_exp *, int, int)); static void add_frag PARAMS ((symbolS *, offsetT, int)); -/* Like addword, but goes BEFORE general operands */ +/* Like addword, but goes BEFORE general operands. */ + static void insop (w, opcode) int w; @@ -432,10 +430,10 @@ static const int n_archs = sizeof (archs) / sizeof (archs[0]); BYTE and SHORT forms, punting if that isn't enough. This gives us four different relaxation modes for branches: */ -#define BRANCHBWL 0 /* branch byte, word, or long */ -#define BRABSJUNC 1 /* absolute jump for LONG, unconditional */ -#define BRABSJCOND 2 /* absolute jump for LONG, conditional */ -#define BRANCHBW 3 /* branch byte or word */ +#define BRANCHBWL 0 /* Branch byte, word, or long. */ +#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */ +#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */ +#define BRANCHBW 3 /* Branch byte or word. */ /* We also relax coprocessor branches and DBcc's. All CPUs that support coprocessor branches support them in word and long forms, so we have only @@ -445,9 +443,9 @@ static const int n_archs = sizeof (archs) / sizeof (archs[0]); This gives us two relaxation modes. If long branches are not available and absolute jumps are not acceptable, we don't relax DBcc's. */ -#define FBRANCH 4 /* coprocessor branch */ -#define DBCCLBR 5 /* DBcc relaxable with a long branch */ -#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump */ +#define FBRANCH 4 /* Coprocessor branch. */ +#define DBCCLBR 5 /* DBcc relaxable with a long branch. */ +#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */ /* That's all for instruction relaxation. However, we also relax PC-relative operands. Specifically, we have three operand relaxation modes. On the @@ -460,9 +458,9 @@ static const int n_archs = sizeof (archs) / sizeof (archs[0]); form of the PC+displacement+index operand. Finally, some absolute operands can be relaxed down to 16-bit PC-relative. */ -#define PCREL1632 7 /* 16-bit or 32-bit PC-relative */ -#define PCINDEX 8 /* PC+displacement+index */ -#define ABSTOPCREL 9 /* absolute relax down to 16-bit PC-relative */ +#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */ +#define PCINDEX 8 /* PC + displacement + index. */ +#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */ /* Note that calls to frag_var need to specify the maximum expansion needed; this is currently 10 bytes for DBCC. */ @@ -496,22 +494,22 @@ relax_typeS md_relax_table[] = { 1, 1, 0, 0 }, { 1, 1, 0, 0 }, - { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */ + { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */ { 32767, -32768, 2, TAB (FBRANCH, LONG) }, { 0, 0, 4, 0 }, { 1, 1, 0, 0 }, - { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */ + { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ { 32767, -32768, 2, TAB (DBCCLBR, LONG) }, { 0, 0, 10, 0 }, { 1, 1, 0, 0 }, - { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */ + { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ { 32767, -32768, 2, TAB (DBCCABSJ, LONG) }, { 0, 0, 10, 0 }, { 1, 1, 0, 0 }, - { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE */ + { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */ { 32767, -32768, 2, TAB (PCREL1632, LONG) }, { 0, 0, 6, 0 }, { 1, 1, 0, 0 }, @@ -521,7 +519,7 @@ relax_typeS md_relax_table[] = { 0, 0, 4, 0 }, { 1, 1, 0, 0 }, - { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE */ + { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */ { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) }, { 0, 0, 4, 0 }, { 1, 1, 0, 0 }, @@ -529,15 +527,13 @@ relax_typeS md_relax_table[] = /* These are the machine dependent pseudo-ops. These are included so the assembler can work on the output from the SUN C compiler, which - generates these. - */ + generates these. */ /* This table describes all the machine specific pseudo-ops the assembler has to support. The fields are: pseudo-op name without dot function to call to execute this pseudo-op - Integer arg to pass to the function - */ + Integer arg to pass to the function. */ const pseudo_typeS md_pseudo_table[] = { {"data1", s_data1, 0}, @@ -661,17 +657,20 @@ make_pcrel_absolute(fixP, add_number) { register unsigned char *opcode = fixP->fx_frag->fr_opcode; - /* rewrite the PC relative instructions to absolute address ones. - * these are rumoured to be faster, and the apollo linker refuses - * to deal with the PC relative relocations. - */ - if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */ + /* Rewrite the PC relative instructions to absolute address ones. + these are rumoured to be faster, and the apollo linker refuses + to deal with the PC relative relocations. */ + if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */ { + if (flag_keep_pcrel) + as_fatal(_("Tried to convert PC relative branch to absolute jump")); opcode[0] = 0x4e; opcode[1] = 0xf9; } - else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */ + else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */ { + if (flag_keep_pcrel) + as_fatal(_("Tried to convert PC relative BSR to absolute JSR")); opcode[0] = 0x4e; opcode[1] = 0xb9; } @@ -839,7 +838,7 @@ int tc_m68k_fix_adjustable (fixP) fixS *fixP; { - /* adjust_reloc_syms doesn't know about the GOT */ + /* Adjust_reloc_syms doesn't know about the GOT. */ switch (fixP->fx_r_type) { case BFD_RELOC_8_GOT_PCREL: @@ -1014,7 +1013,7 @@ m68k_ip (instring) unsigned long ok_arch = 0; if (*instring == ' ') - instring++; /* skip leading whitespace */ + instring++; /* Skip leading whitespace. */ /* Scan up to end of operation-code, which MUST end in end-of-string or exactly 1 space. */ @@ -1063,7 +1062,7 @@ m68k_ip (instring) return; } - /* found a legitimate opcode, start matching operands */ + /* Found a legitimate opcode, start matching operands. */ while (*p == ' ') ++p; @@ -1072,7 +1071,7 @@ m68k_ip (instring) char *old = input_line_pointer; *old = '\n'; input_line_pointer = p; - /* Ahh - it's a motorola style psuedo op */ + /* Ahh - it's a motorola style psuedo op. */ mote_pseudo_table[opcode->m_opnum].poc_handler (mote_pseudo_table[opcode->m_opnum].poc_val); input_line_pointer = old; @@ -1122,7 +1121,7 @@ m68k_ip (instring) opsfound++; } - /* We've got the operands. Find an opcode that'll accept them */ + /* We've got the operands. Find an opcode that'll accept them. */ for (losing = 0;;) { /* If we didn't get the right number of ops, or we have no @@ -1710,7 +1709,7 @@ m68k_ip (instring) Don't forget that you need these operands to use 68030 MMU instructions. */ #ifndef NO_68851 - /* Memory addressing mode used by pflushr */ + /* Memory addressing mode used by pflushr. */ case '|': if (opP->mode == CONTROL || opP->mode == FPREG @@ -1787,9 +1786,7 @@ m68k_ip (instring) && opP->reg != IC && opP->reg != DC && opP->reg != BC)) - { - losing++; - } /* not a cache specifier. */ + losing++; break; case '_': @@ -1812,17 +1809,15 @@ m68k_ip (instring) default: abort (); - } /* switch on type of operand */ + } if (losing) break; - } /* for each operand */ - } /* if immediately wrong */ + } + } if (!losing) - { - break; - } /* got it. */ + break; opcode = opcode->m_next; @@ -1882,13 +1877,12 @@ m68k_ip (instring) else the_ins.error = _("operands mismatch"); return; - } /* Fell off the end */ + } losing = 0; } - /* now assemble it */ - + /* Now assemble it. */ the_ins.args = opcode->m_operands; the_ins.numargs = opcode->m_opnum; the_ins.numo = opcode->m_codenum; @@ -1981,7 +1975,7 @@ m68k_ip (instring) if (!baseo) break; - /* We gotta put out some float */ + /* We gotta put out some float. */ if (op (&opP->disp) != O_big) { valueT val; @@ -2055,7 +2049,7 @@ m68k_ip (instring) #endif } - /* Force into index mode. Hope this works */ + /* Force into index mode. Hope this works. */ /* We do the first bit for 32-bit displacements, and the second bit for 16 bit ones. It is possible that we @@ -2166,7 +2160,7 @@ m68k_ip (instring) else siz2 = SIZE_UNSPEC; - /* Index register stuff */ + /* Index register stuff. */ if (opP->index.reg != 0 && opP->index.reg >= DATA && opP->index.reg <= ADDR7) @@ -2277,7 +2271,7 @@ m68k_ip (instring) } else { - nextword |= 0x40; /* No index reg */ + nextword |= 0x40; /* No index reg. */ if (opP->index.reg >= ZDATA0 && opP->index.reg <= ZDATA7) nextword |= (opP->index.reg - ZDATA0) << 12; @@ -2325,7 +2319,7 @@ m68k_ip (instring) break; } - /* Figure out innner displacement stuff */ + /* Figure out innner displacement stuff. */ if (opP->mode == POST || opP->mode == PRE) { if (cpu_of_arch (current_architecture) & cpu32) @@ -2415,7 +2409,7 @@ m68k_ip (instring) TAB (ABSTOPCREL, SZ_UNDEF)); break; } - /* Fall through into long */ + /* Fall through into long. */ case SIZE_LONG: if (isvar (&opP->disp)) add_fix ('l', &opP->disp, 0, 0); @@ -2428,7 +2422,8 @@ m68k_ip (instring) case SIZE_BYTE: as_bad (_("unsupported byte value; use a different suffix")); /* Fall through. */ - case SIZE_WORD: /* Word */ + + case SIZE_WORD: if (isvar (&opP->disp)) add_fix ('w', &opP->disp, 0, 0); @@ -2548,7 +2543,7 @@ m68k_ip (instring) addword (0); break; case 'g': - if (subs (&opP->disp)) /* We can't relax it */ + if (subs (&opP->disp)) /* We can't relax it. */ goto long_branch; #ifdef OBJ_ELF @@ -2621,12 +2616,12 @@ m68k_ip (instring) } addword (0); break; - case 'C': /* Fixed size LONG coproc branches */ + case 'C': /* Fixed size LONG coproc branches. */ add_fix ('l', &opP->disp, 1, 0); addword (0); addword (0); break; - case 'c': /* Var size Coprocesssor branches */ + case 'c': /* Var size Coprocesssor branches. */ if (subs (&opP->disp) || (adds (&opP->disp) == 0)) { the_ins.opcode[the_ins.numo - 1] |= 0x40; @@ -2643,10 +2638,10 @@ m68k_ip (instring) } break; - case 'C': /* Ignore it */ + case 'C': /* Ignore it. */ break; - case 'd': /* JF this is a kludge */ + case 'd': /* JF this is a kludge. */ install_operand ('s', opP->reg - ADDR); tmpreg = get_num (&opP->disp, 80); if (!issword (tmpreg)) @@ -2661,14 +2656,14 @@ m68k_ip (instring) install_operand (s[1], opP->reg - DATA); break; - case 'E': /* Ignore it */ + case 'E': /* Ignore it. */ break; case 'F': install_operand (s[1], opP->reg - FP0); break; - case 'G': /* Ignore it */ + case 'G': /* Ignore it. */ case 'H': break; @@ -2677,7 +2672,7 @@ m68k_ip (instring) install_operand (s[1], tmpreg); break; - case 'J': /* JF foo */ + case 'J': /* JF foo. */ switch (opP->reg) { case SFC: @@ -2818,7 +2813,7 @@ m68k_ip (instring) case 'R': /* This depends on the fact that ADDR registers are eight more than their corresponding DATA regs, so the result - will have the ADDR_REG bit set */ + will have the ADDR_REG bit set. */ install_operand (s[1], opP->reg - DATA); break; @@ -2841,14 +2836,14 @@ m68k_ip (instring) install_operand (s[1], tmpreg); break; - case 'S': /* Ignore it */ + case 'S': /* Ignore it. */ break; case 'T': install_operand (s[1], get_num (&opP->disp, 30)); break; - case 'U': /* Ignore it */ + case 'U': /* Ignore it. */ break; case 'c': @@ -2868,7 +2863,7 @@ m68k_ip (instring) break; default: as_fatal (_("failed sanity check")); - } /* switch on cache token */ + } /* switch on cache token. */ install_operand (s[1], tmpreg); break; #ifndef NO_68851 @@ -2992,7 +2987,7 @@ m68k_ip (instring) tmpreg = get_num (&opP->disp, 20); install_operand (s[1], tmpreg); break; - case '_': /* used only for move16 absolute 32-bit address */ + case '_': /* used only for move16 absolute 32-bit address. */ if (isvar (&opP->disp)) add_fix ('l', &opP->disp, 0, 0); tmpreg = get_num (&opP->disp, 80); @@ -3002,7 +2997,7 @@ m68k_ip (instring) case 'u': install_operand (s[1], opP->reg - DATA0L); opP->reg -= (DATA0L); - opP->reg &= 0x0F; /* remove upper/lower bit */ + opP->reg &= 0x0F; /* remove upper/lower bit. */ break; default: abort (); @@ -3071,7 +3066,7 @@ install_operand (mode, val) switch (mode) { case 's': - the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */ + the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */ break; case 'd': the_ins.opcode[0] |= val << 9; @@ -3126,7 +3121,7 @@ install_operand (mode, val) break; case 'j': the_ins.opcode[1] |= val; - the_ins.numo++; /* What a hack */ + the_ins.numo++; /* What a hack. */ break; case 'k': the_ins.opcode[1] |= val << 4; @@ -3196,7 +3191,7 @@ install_gen_operand (mode, val) case 'p': the_ins.opcode[0] |= val; break; - /* more stuff goes here */ + /* more stuff goes here. */ default: as_fatal (_("failed sanity check.")); } @@ -3231,7 +3226,7 @@ crack_operand (str, opP) else if (*str == ')') { if (!parens) - { /* ERROR */ + { /* ERROR. */ opP->error = _("Extra )"); return str; } @@ -3242,7 +3237,7 @@ crack_operand (str, opP) inquote = ! inquote; } if (!*str && parens) - { /* ERROR */ + { /* ERROR. */ opP->error = _("Missing )"); return str; } @@ -3255,7 +3250,7 @@ crack_operand (str, opP) } *str = c; if (c == '}') - c = *++str; /* JF bitfield hack */ + c = *++str; /* JF bitfield hack. */ if (c) { c = *++str; @@ -3372,53 +3367,53 @@ static const struct init_entry init_table[] = { "macsr", MACSR }, { "mask", MASK }, - /* control registers */ - { "sfc", SFC }, /* Source Function Code */ + /* Control registers. */ + { "sfc", SFC }, /* Source Function Code. */ { "sfcr", SFC }, - { "dfc", DFC }, /* Destination Function Code */ + { "dfc", DFC }, /* Destination Function Code. */ { "dfcr", DFC }, - { "cacr", CACR }, /* Cache Control Register */ - { "caar", CAAR }, /* Cache Address Register */ + { "cacr", CACR }, /* Cache Control Register. */ + { "caar", CAAR }, /* Cache Address Register. */ - { "usp", USP }, /* User Stack Pointer */ - { "vbr", VBR }, /* Vector Base Register */ - { "msp", MSP }, /* Master Stack Pointer */ - { "isp", ISP }, /* Interrupt Stack Pointer */ + { "usp", USP }, /* User Stack Pointer. */ + { "vbr", VBR }, /* Vector Base Register. */ + { "msp", MSP }, /* Master Stack Pointer. */ + { "isp", ISP }, /* Interrupt Stack Pointer. */ - { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */ - { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */ - { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */ - { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */ + { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */ + { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */ + { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */ + { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */ /* 68ec040 versions of same */ - { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */ - { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */ - { "dacr0", DTT0 }, /* Data Access Control Register 0 */ - { "dacr1", DTT1 }, /* Data Access Control Register 0 */ + { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */ + { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */ + { "dacr0", DTT0 }, /* Data Access Control Register 0. */ + { "dacr1", DTT1 }, /* Data Access Control Register 0. */ /* mcf5200 versions of same. The ColdFire programmer's reference manual indicated that the order is 2,3,0,1, but Ken Rose <rose@netcom.com> says that 0,1,2,3 is the correct order. */ - { "acr0", ITT0 }, /* Access Control Unit 0 */ - { "acr1", ITT1 }, /* Access Control Unit 1 */ - { "acr2", DTT0 }, /* Access Control Unit 2 */ - { "acr3", DTT1 }, /* Access Control Unit 3 */ + { "acr0", ITT0 }, /* Access Control Unit 0. */ + { "acr1", ITT1 }, /* Access Control Unit 1. */ + { "acr2", DTT0 }, /* Access Control Unit 2. */ + { "acr3", DTT1 }, /* Access Control Unit 3. */ - { "tc", TC }, /* MMU Translation Control Register */ + { "tc", TC }, /* MMU Translation Control Register. */ { "tcr", TC }, - { "mmusr", MMUSR }, /* MMU Status Register */ - { "srp", SRP }, /* User Root Pointer */ - { "urp", URP }, /* Supervisor Root Pointer */ + { "mmusr", MMUSR }, /* MMU Status Register. */ + { "srp", SRP }, /* User Root Pointer. */ + { "urp", URP }, /* Supervisor Root Pointer. */ { "buscr", BUSCR }, { "pcr", PCR }, - { "rombar", ROMBAR }, /* ROM Base Address Register */ - { "rambar0", RAMBAR0 }, /* ROM Base Address Register */ - { "rambar1", RAMBAR1 }, /* ROM Base Address Register */ - { "mbar", MBAR }, /* Module Base Address Register */ - /* end of control registers */ + { "rombar", ROMBAR }, /* ROM Base Address Register. */ + { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */ + { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */ + { "mbar", MBAR }, /* Module Base Address Register. */ + /* End of control registers. */ { "ac", AC }, { "bc", BC }, @@ -3452,10 +3447,10 @@ static const struct init_entry init_table[] = { "tt0", TT0 }, { "tt1", TT1 }, - /* 68ec030 versions of same */ + /* 68ec030 versions of same. */ { "ac0", TT0 }, { "ac1", TT1 }, - /* 68ec030 access control unit, identical to 030 MMU status reg */ + /* 68ec030 access control unit, identical to 030 MMU status reg. */ { "acusr", PSR }, /* Suppressed data and address registers. */ @@ -3610,7 +3605,7 @@ md_assemble (str) if (the_ins.nfrag == 0) { - /* No frag hacking involved; just put it out */ + /* No frag hacking involved; just put it out. */ toP = frag_more (2 * the_ins.numo); fromP = &the_ins.opcode[0]; for (m = the_ins.numo; m; --m) @@ -3619,7 +3614,7 @@ md_assemble (str) toP += 2; fromP++; } - /* put out symbol-dependent info */ + /* Put out symbol-dependent info. */ for (m = 0; m < the_ins.nrel; m++) { switch (the_ins.reloc[m].wid) @@ -3660,7 +3655,7 @@ md_assemble (str) return; } - /* There's some frag hacking */ + /* There's some frag hacking. */ { /* Calculate the max frag size. */ int wid; @@ -3772,7 +3767,7 @@ md_begin () const struct m68k_opcode *ins; struct m68k_incant *hack, *slak; - const char *retval = 0; /* empty string, or error msg text */ + const char *retval = 0; /* Empty string, or error msg text. */ int i; if (flag_mri) @@ -3798,7 +3793,7 @@ md_begin () slak->m_opnum = strlen (slak->m_operands) / 2; slak->m_arch = ins->arch; slak->m_opcode = ins->opcode; - /* This is kludgey */ + /* This is kludgey. */ slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1; if (i + 1 != m68k_numopcodes && !strcmp (ins->name, m68k_opcodes[i + 1].name)) @@ -3914,7 +3909,7 @@ md_begin () #ifndef MIT_SYNTAX_ONLY /* Insert pseudo ops, these have to go into the opcode table since - gas expects pseudo ops to start with a dot */ + gas expects pseudo ops to start with a dot. */ { int n = 0; while (mote_pseudo_table[n].poc_name) @@ -4147,7 +4142,7 @@ m68k_mri_mode_change (on) } } -/* Equal to MAX_PRECISION in atof-ieee.c */ +/* Equal to MAX_PRECISION in atof-ieee.c. */ #define MAX_LITTLENUMS 6 /* Turn a string in input_line_pointer into a floating point constant @@ -4232,7 +4227,7 @@ md_apply_fix3 (fixP, valP, seg) to generate the code we want. */ char *buf = fixP->fx_frag->fr_literal; buf += fixP->fx_where; - /* end ibm compiler workaround */ + /* End ibm compiler workaround. */ val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; @@ -4243,7 +4238,7 @@ md_apply_fix3 (fixP, valP, seg) if (fixP->fx_addsy) { memset (buf, 0, fixP->fx_size); - fixP->fx_addnumber = val; /* Remember value for emit_reloc */ + fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT && !S_IS_DEFINED (fixP->fx_addsy) @@ -4280,7 +4275,7 @@ md_apply_fix3 (fixP, valP, seg) *buf++ = (val >> 8); *buf++ = val; upper_limit = 0x7fffffff; - lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */ + lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */ break; default: BAD_CASE (fixP->fx_size); @@ -4341,7 +4336,7 @@ md_convert_frag_1 (fragP) want. */ register char *buffer_address = fragP->fr_literal; buffer_address += fragP->fr_fix; - /* end ibm compiler workaround */ + /* End ibm compiler workaround. */ /* The displacement of the address, from current location. */ disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; @@ -4379,16 +4374,20 @@ md_convert_frag_1 (fragP) case TAB (BRABSJUNC, LONG): if (fragP->fr_opcode[0] == 0x61) /* jbsr */ { + if (flag_keep_pcrel) + as_fatal(_("Tried to convert PC relative BSR to absolute JSR")); fragP->fr_opcode[0] = 0x4E; - fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */ + fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0, RELAX_RELOC_ABS32); fragP->fr_fix += 4; } else if (fragP->fr_opcode[0] == 0x60) /* jbra */ { + if (flag_keep_pcrel) + as_fatal(_("Tried to convert PC relative branch to absolute jump")); fragP->fr_opcode[0] = 0x4E; - fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */ + fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0, RELAX_RELOC_ABS32); fragP->fr_fix += 4; @@ -4401,18 +4400,20 @@ md_convert_frag_1 (fragP) } break; case TAB (BRABSJCOND, LONG): - /* Only Bcc 68000 instructions can come here. */ - /* Change bcc into b!cc/jmp absl long. */ + if (flag_keep_pcrel) + as_fatal(_("Tried to convert PC relative conditional branch to absolute jump")); - fragP->fr_opcode[0] ^= 0x01; /* invert bcc */ - fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */ + /* Only Bcc 68000 instructions can come here + Change bcc into b!cc/jmp absl long. */ + fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */ + fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */ /* JF: these used to be fr_opcode[2,3], but they may be in a different frag, in which case refering to them is a no-no. Only fr_opcode[0,1] are guaranteed to work. */ *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ *buffer_address++ = (char) 0xf9; - fragP->fr_fix += 2; /* account for jmp instruction */ + fragP->fr_fix += 2; /* Account for jmp instruction. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0, RELAX_RELOC_ABS32); fragP->fr_fix += 4; @@ -4424,7 +4425,7 @@ md_convert_frag_1 (fragP) fragP->fr_fix += 2; break; case TAB (FBRANCH, LONG): - fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */ + fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1, RELAX_RELOC_PC32); fragP->fr_fix += 4; @@ -4436,35 +4437,39 @@ md_convert_frag_1 (fragP) fragP->fr_fix += 2; break; case TAB (DBCCLBR, LONG): - /* only DBcc instructions can come here */ - /* Change dbcc into dbcc/bral. */ + /* Only DBcc instructions can come here. + Change dbcc into dbcc/bral. + JF: these used to be fr_opcode[2-7], but that's wrong. */ + if (flag_keep_pcrel) + as_fatal(_("Tried to convert DBcc to absolute jump")); - /* JF: these used to be fr_opcode[2-7], but that's wrong */ - *buffer_address++ = 0x00; /* branch offset = 4 */ + *buffer_address++ = 0x00; /* Branch offset = 4. */ *buffer_address++ = 0x04; - *buffer_address++ = 0x60; /* put in bra pc+6 */ + *buffer_address++ = 0x60; /* Put in bra pc+6. */ *buffer_address++ = 0x06; *buffer_address++ = 0x60; /* Put in bral (0x60ff). */ *buffer_address++ = (char) 0xff; - fragP->fr_fix += 6; /* account for bra/jmp instructions */ + fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1, RELAX_RELOC_PC32); fragP->fr_fix += 4; break; case TAB (DBCCABSJ, LONG): - /* only DBcc instructions can come here */ - /* Change dbcc into dbcc/jmp. */ + /* Only DBcc instructions can come here. + Change dbcc into dbcc/jmp. + JF: these used to be fr_opcode[2-7], but that's wrong. */ + if (flag_keep_pcrel) + as_fatal(_("Tried to convert PC relative conditional branch to absolute jump")); - /* JF: these used to be fr_opcode[2-7], but that's wrong */ - *buffer_address++ = 0x00; /* branch offset = 4 */ + *buffer_address++ = 0x00; /* Branch offset = 4. */ *buffer_address++ = 0x04; - *buffer_address++ = 0x60; /* put in bra pc+6 */ + *buffer_address++ = 0x60; /* Put in bra pc + 6. */ *buffer_address++ = 0x06; - *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ + *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ *buffer_address++ = (char) 0xf9; - fragP->fr_fix += 6; /* account for bra/jmp instructions */ + fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0, RELAX_RELOC_ABS32); fragP->fr_fix += 4; @@ -4518,8 +4523,10 @@ md_convert_frag_1 (fragP) fragP->fr_fix += 2; break; case TAB (ABSTOPCREL, LONG): + if (flag_keep_pcrel) + as_fatal(_("Tried to convert PC relative conditional branch to absolute jump")); /* The thing to do here is force it to ABSOLUTE LONG, since - ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */ + ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */ if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) abort (); fragP->fr_opcode[1] &= ~0x3F; @@ -4689,7 +4696,7 @@ md_estimate_size_before_relax (fragP, segment) /* the bit-field entries in the relocation_info struct plays hell with the byte-order problems of cross-assembly. So as a hack, I added this mach. dependent ri twiddler. Ugly, but it gets - you there. -KWK */ + you there. -KWK */ /* on m68k: first 4 bytes are normal unsigned long, next three bytes are symbolnum, most sig. byte first. Last byte is broken up with bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower @@ -4702,17 +4709,17 @@ md_ri_to_chars (the_bytes, ri) char *the_bytes; struct reloc_info_generic *ri; { - /* this is easy */ + /* This is easy. */ md_number_to_chars (the_bytes, ri->r_address, 4); - /* now the fun stuff */ + /* Now the fun stuff. */ the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff; - the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; - the_bytes[6] = ri->r_symbolnum & 0x0ff; + the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; + the_bytes[6] = ri->r_symbolnum & 0x0ff; the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) | ((ri->r_extern << 4) & 0x10)); } -#endif /* comment */ +#endif #ifndef BFD_ASSEMBLER void @@ -4779,6 +4786,8 @@ md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) if (!HAVE_LONG_BRANCH(current_architecture)) { + if (flag_keep_pcrel) + as_fatal(_("Tried to convert PC relative branch to absolute jump")); offset = to_addr - S_GET_VALUE (to_symbol); md_number_to_chars (ptr, (valueT) 0x4EF9, 2); md_number_to_chars (ptr + 2, (valueT) offset, 4); @@ -4818,7 +4827,7 @@ get_num (exp, ok) { if (exp->exp.X_op == O_absent) { - /* Do the same thing the VAX asm does */ + /* Do the same thing the VAX asm does. */ op (exp) = O_constant; adds (exp) = 0; subs (exp) = 0; @@ -4878,18 +4887,18 @@ get_num (exp, ok) } else if (exp->exp.X_op == O_big) { - if (offs (exp) <= 0 /* flonum */ - && (ok == 80 /* no bignums */ - || (ok > 10 /* small-int ranges including 0 ok */ + if (offs (exp) <= 0 /* flonum. */ + && (ok == 80 /* no bignums. */ + || (ok > 10 /* Small-int ranges including 0 ok. */ /* If we have a flonum zero, a zero integer should do as well (e.g., in moveq). */ && generic_floating_point_number.exponent == 0 && generic_floating_point_number.low[0] == 0))) { - /* HACK! Turn it into a long */ + /* HACK! Turn it into a long. */ LITTLENUM_TYPE words[6]; - gen_to_words (words, 2, 8L); /* These numbers are magic! */ + gen_to_words (words, 2, 8L); /* These numbers are magic! */ op (exp) = O_constant; adds (exp) = 0; subs (exp) = 0; @@ -5737,10 +5746,10 @@ swap_mri_condition (cc) { case MCC ('h', 'i'): return MCC ('c', 's'); case MCC ('l', 's'): return MCC ('c', 'c'); - /* <HS> is an alias for <CC> */ + /* <HS> is an alias for <CC>. */ case MCC ('h', 's'): case MCC ('c', 'c'): return MCC ('l', 's'); - /* <LO> is an alias for <CS> */ + /* <LO> is an alias for <CS>. */ case MCC ('l', 'o'): case MCC ('c', 's'): return MCC ('h', 'i'); case MCC ('p', 'l'): return MCC ('m', 'i'); @@ -5749,7 +5758,7 @@ swap_mri_condition (cc) case MCC ('l', 't'): return MCC ('g', 't'); case MCC ('g', 't'): return MCC ('l', 't'); case MCC ('l', 'e'): return MCC ('g', 'e'); - /* issue a warning for conditions we can not swap */ + /* Issue a warning for conditions we can not swap. */ case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem case MCC ('v', 'c'): @@ -6043,7 +6052,7 @@ s_mri_if (qual) or at first column of a line (I think this can't actually happen here?) This is important when assembling: if d0 <ne> 12(a0,d0*2) then - if d0 <ne> #CONST*20 then */ + if d0 <ne> #CONST*20 then. */ while ( ! ( is_end_of_line[(unsigned char) *s] || ( flag_mri && *s == '*' @@ -6438,12 +6447,11 @@ s_mri_for (qual) } /* We have fully parsed the FOR operands. Now build the loop. */ - n = push_mri_control (mri_for); buf = (char *) xmalloc (50 + (input_line_pointer - varstart)); - /* move init,var */ + /* Move init,var. */ s = buf; *s++ = 'm'; *s++ = 'o'; @@ -6462,7 +6470,7 @@ s_mri_for (qual) colon (n->top); - /* cmp end,var */ + /* cmp end,var. */ s = buf; *s++ = 'c'; *s++ = 'm'; @@ -6478,7 +6486,7 @@ s_mri_for (qual) *s = '\0'; mri_assemble (buf); - /* bcc bottom */ + /* bcc bottom. */ ex[0] = TOLOWER (extent); ex[1] = '\0'; if (up) @@ -6622,7 +6630,7 @@ s_mri_while (qual) or at first column of a line (I think this can't actually happen here?) This is important when assembling: while d0 <ne> 12(a0,d0*2) do - while d0 <ne> #CONST*20 do */ + while d0 <ne> #CONST*20 do. */ while (! (is_end_of_line[(unsigned char) *s] || (flag_mri && *s == '*' @@ -6760,7 +6768,7 @@ md_parse_option (c, arg) switch (c) { case 'l': /* -l means keep external to 2 bit offset - rather than 16 bit one */ + rather than 16 bit one. */ flag_short_refs = 1; break; @@ -6777,7 +6785,7 @@ md_parse_option (c, arg) case 'A': if (*arg == 'm') arg++; - /* intentional fall-through */ + /* Intentional fall-through. */ case 'm': if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-') @@ -6853,7 +6861,7 @@ md_parse_option (c, arg) case OPTION_PIC: case 'k': flag_want_pic = 1; - break; /* -pic, Position Independent Code */ + break; /* -pic, Position Independent Code. */ case OPTION_REGISTER_PREFIX_OPTIONAL: flag_reg_prefix_optional = 1; @@ -6969,8 +6977,8 @@ md_show_usage (stream) #ifdef TEST2 /* TEST2: Test md_assemble() */ -/* Warning, this routine probably doesn't work anymore */ - +/* Warning, this routine probably doesn't work anymore. */ +int main () { struct m68k_it the_ins; @@ -7139,7 +7147,7 @@ tc_coff_sizemachdep (frag) void m68k_elf_final_processing () { - /* Set file-specific flags if this is a cpu32 processor */ + /* Set file-specific flags if this is a cpu32 processor. */ if (cpu_of_arch (current_architecture) & cpu32) elf_elfheader (stdoutput)->e_flags |= EF_CPU32; else if ((cpu_of_arch (current_architecture) & m68000up) |