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-rw-r--r--gas/doc/c-arc.texi26
1 files changed, 13 insertions, 13 deletions
diff --git a/gas/doc/c-arc.texi b/gas/doc/c-arc.texi
index ea0fa4eb52..ec7eff4e66 100644
--- a/gas/doc/c-arc.texi
+++ b/gas/doc/c-arc.texi
@@ -151,10 +151,10 @@ using this directive. The first parameter is the @var{name} of the
new auxiallry register. The second parameter is the @var{address} of
the register in the auxiliary register memory map for the variant of
the ARC. The third parameter specifies the @var{mode} in which the
-register can be operated is and it can be one of:
+register can be operated is and it can be one of:
@table @code
-@item r (readonly)
+@item r (readonly)
@item w (write only)
@item r|w (read or write)
@end table
@@ -178,7 +178,7 @@ specify extra condition codes with any values. For example:
@smallexample
.extCondCode is_busy,0x14
-
+
add.is_busy r1,r2,r3
bis_busy _main
@end smallexample
@@ -187,10 +187,10 @@ specify extra condition codes with any values. For example:
@item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut}
Specifies an extension core register @var{name} for the application.
This allows a register @var{name} with a valid @var{regnum} between 0
-and 60, with the following as valid values for @var{mode}
+and 60, with the following as valid values for @var{mode}
@table @samp
-@item @emph{r} (readonly)
+@item @emph{r} (readonly)
@item @emph{w} (write only)
@item @emph{r|w} (read or write)
@end table
@@ -222,7 +222,7 @@ by the user. The parameters are:
@table @bullet
@item @var{name}
-Name of the extension instruction
+Name of the extension instruction
@item @var{opcode}
Opcode to be used. (Bits 27:31 in the encoding). Valid values
@@ -234,7 +234,7 @@ correct value also depends on @var{syntaxclass}
@item @var{suffixclass}
Determines the kinds of suffixes to be allowed. Valid values are
-@code{SUFFIX_NONE}, @code{SUFFIX_COND},
+@code{SUFFIX_NONE}, @code{SUFFIX_COND},
@code{SUFFIX_FLAG} which indicates the absence or presence of
conditional suffixes and flag setting by the extension instruction.
It is also possible to specify that an instruction sets the flags and
@@ -246,9 +246,9 @@ following values:
@table @code
@item @code{SYNTAX_2OP}:
-2 Operand Instruction
+2 Operand Instruction
@item @code{SYNTAX_3OP}:
-3 Operand Instruction
+3 Operand Instruction
@end table
In addition there could be modifiers for the syntax class as described
@@ -262,7 +262,7 @@ Modifies syntax class SYNTAX_3OP, specifying that the first operand
of a three-operand instruction must be an immediate (i.e., the result
is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with
SYNTAX_3OP as given in the example below. This could usually be used
-to set the flags using specific instructions and not retain results.
+to set the flags using specific instructions and not retain results.
@item @code{OP1_IMM_IMPLIED}:
Modifies syntax class SYNTAX_20P, it specifies that there is an
@@ -270,7 +270,7 @@ implied immediate destination operand which does not appear in the
syntax. For example, if the source code contains an instruction like:
@smallexample
-inst r1,r2
+inst r1,r2
@end smallexample
it really means that the first argument is an implied immediate (that
@@ -278,7 +278,7 @@ is, the result is discarded). This is the same as though the source
code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it
with SYNTAX_20P.
-@end itemize
+@end itemize
@end table
For example, defining 64-bit multiplier with immediate operands:
@@ -290,7 +290,7 @@ For example, defining 64-bit multiplier with immediate operands:
The above specifies an extension instruction called mp64 which has 3 operands,
sets the flags, can be used with a condition code, for which the
-first operand is an immediate. (Equivalent to discarding the result
+first operand is an immediate. (Equivalent to discarding the result
of the operation).
@smallexample