diff options
Diffstat (limited to 'gas/doc/c-arm.texi')
| -rw-r--r-- | gas/doc/c-arm.texi | 62 |
1 files changed, 31 insertions, 31 deletions
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi index 7d622efb65..983434f166 100644 --- a/gas/doc/c-arm.texi +++ b/gas/doc/c-arm.texi @@ -38,7 +38,7 @@ This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are -recognized: +recognized: @code{arm1}, @code{arm2}, @code{arm250}, @@ -131,25 +131,25 @@ recognized: @code{i80200} (Intel XScale processor) @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) and -@code{xscale}. +@code{xscale}. The special name @code{all} may be used to allow the assembler to accept instructions valid for any ARM processor. -In addition to the basic instruction set, the assembler can be told to -accept various extension mnemonics that extend the processor using the +In addition to the basic instruction set, the assembler can be told to +accept various extension mnemonics that extend the processor using the co-processor instruction space. For example, @code{-mcpu=arm920+maverick} -is equivalent to specifying @code{-mcpu=ep9312}. +is equivalent to specifying @code{-mcpu=ep9312}. -Multiple extensions may be specified, separated by a @code{+}. The +Multiple extensions may be specified, separated by a @code{+}. The extensions should be specified in ascending alphabetical order. -Some extensions may be restricted to particular architectures; this is +Some extensions may be restricted to particular architectures; this is documented in the list of extensions below. -Extension mnemonics may also be removed from those the assembler accepts. -This is done be prepending @code{no} to the option that adds the extension. -Extensions that are removed should be listed after all extensions which have -been added, again in ascending alphabetical order. For example, +Extension mnemonics may also be removed from those the assembler accepts. +This is done be prepending @code{no} to the option that adds the extension. +Extensions that are removed should be listed after all extensions which have +been added, again in ascending alphabetical order. For example, @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}. @@ -164,7 +164,7 @@ The following extensions are currently supported: @code{os} (Operating System for v6M architecture), @code{sec} (Security Extensions for v6K and v7-A architectures), @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}), -@code{virt} (Virtualization Extensions for v7-A architecture, implies +@code{virt} (Virtualization Extensions for v7-A architecture, implies @code{idiv}), and @code{xscale}. @@ -173,8 +173,8 @@ and @item -march=@var{architecture}[+@var{extension}@dots{}] This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which -will not execute on the target architecture. The following architecture -names are recognized: +will not execute on the target architecture. The following architecture +names are recognized: @code{armv1}, @code{armv2}, @code{armv2a}, @@ -218,7 +218,7 @@ extension options as the @code{-mcpu} option. This option specifies the floating point format to assemble for. The assembler will issue an error message if an attempt is made to assemble -an instruction which will not execute on the target floating point unit. +an instruction which will not execute on the target floating point unit. The following format options are recognized: @code{softfpa}, @code{fpe}, @@ -260,14 +260,14 @@ In addition to determining which instructions are assembled, this option also affects the way in which the @code{.double} assembler directive behaves when assembling little-endian code. -The default is dependent on the processor selected. For Architecture 5 or -later, the default is to assembler for VFP instructions; for earlier +The default is dependent on the processor selected. For Architecture 5 or +later, the default is to assembler for VFP instructions; for earlier architectures the default is to assemble for FPA instructions. @cindex @code{-mthumb} command line option, ARM @item -mthumb This option specifies that the assembler should start assembling Thumb -instructions; that is, it should behave as though the file starts with a +instructions; that is, it should behave as though the file starts with a @code{.code 16} directive. @cindex @code{-mthumb-interwork} command line option, ARM @@ -303,7 +303,7 @@ Calling Standard. @cindex @code{-matpcs} command line option, ARM @item -matpcs -This option specifies that the output generated by the assembler should +This option specifies that the output generated by the assembler should be marked as supporting the Arm/Thumb Procedure Calling Standard. If enabled this option will cause the assembler to create an empty debugging section in the object file called .arm.atpcs. Debuggers can @@ -546,13 +546,13 @@ boundary). This is for compatibility with ARM's own assembler. Select the target architecture. Valid values for @var{name} are the same as for the @option{-march} commandline option. -Specifying @code{.arch} clears any previously selected architecture +Specifying @code{.arch} clears any previously selected architecture extensions. @cindex @code{.arch_extension} directive, ARM @item .arch_extension @var{name} -Add or remove an architecture extension to the target architecture. Valid -values for @var{name} are the same as those accepted as architectural +Add or remove an architecture extension to the target architecture. Valid +values for @var{name} are the same as those accepted as architectural extensions by the @option{-mcpu} commandline option. @code{.arch_extension} may be used multiple times to add or remove extensions @@ -592,7 +592,7 @@ selects Thumb, with the value 32 selecting ARM. Select the target processor. Valid values for @var{name} are the same as for the @option{-mcpu} commandline option. -Specifying @code{.cpu} clears any previously selected architecture +Specifying @code{.cpu} clears any previously selected architecture extensions. @c DDDDDDDDDDDDDDDDDDDDDDDDDD @@ -658,7 +658,7 @@ The @var{value} is either a @code{number}, @code{"string"}, or @code{number, "string"} depending on the tag. Note - the following legacy values are also accepted by @var{tag}: -@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed}, +@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed}, @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension}, @cindex @code{.even} directive, ARM @@ -950,7 +950,7 @@ used in favour of @code{.save} for saving VFP registers for ARMv6 and above. @cindex opcodes for ARM @code{@value{AS}} implements all the standard ARM opcodes. It also implements several pseudo opcodes, including several synthetic load -instructions. +instructions. @table @code @@ -964,7 +964,7 @@ This pseudo op will always evaluate to a legal ARM instruction that does nothing. Currently it will evaluate to MOV r0, r0. @cindex @code{LDR reg,=<label>} pseudo op, ARM -@item LDR +@item LDR @smallexample ldr <register> , = <expression> @end smallexample @@ -989,7 +989,7 @@ the ADR instruction, then an error will be generated. This instruction will not make use of the literal pool. @cindex @code{ADRL reg,<label>} pseudo op, ARM -@item ADRL +@item ADRL @smallexample adrl <register> <label> @end smallexample @@ -1065,12 +1065,12 @@ that G++ generates for the following C++ input: @verbatim void callee (int *); -int -caller () +int +caller () { int i; callee (&i); - return i; + return i; } @end verbatim @@ -1127,7 +1127,7 @@ The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo op appears immediately before the first instruction of the function while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo op appears immediately after the last instruction of the function. -These pseudo ops specify the range of the function. +These pseudo ops specify the range of the function. Only the order of the other pseudos ops (e.g., @code{.setfp} or @code{.pad}) matters; their exact locations are irrelevant. In the |