diff options
Diffstat (limited to 'gas')
-rw-r--r-- | gas/ChangeLog | 6 | ||||
-rw-r--r-- | gas/config/tc-mips.c | 24 | ||||
-rw-r--r-- | gas/testsuite/ChangeLog | 5 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/mips.exp | 1 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/vr5400-ill.l | 13 | ||||
-rw-r--r-- | gas/testsuite/gas/mips/vr5400-ill.s | 23 |
6 files changed, 61 insertions, 11 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 6b60e2d7da..7e100eb731 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,11 @@ 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling. + (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions. + Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions. + +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p". Require the msb to be <= 31 for "+s". Check that the size is <= 31 for both "+s" and "+S". diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 7acb5e25fc..8fdb124a6b 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -10972,8 +10972,6 @@ validate_mips_insn (const struct mips_opcode *opc) USE_BITS (OP_MASK_RT, OP_SH_RT); break; case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; - case '[': break; - case ']': break; case '1': USE_BITS (OP_MASK_STYPE, OP_SH_STYPE); break; case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break; case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break; @@ -11785,13 +11783,6 @@ mips_ip (char *str, struct mips_cl_insn *ip) continue; break; - case '[': /* These must match exactly. */ - case ']': - gas_assert (!mips_opts.micromips); - if (*s++ == *args) - continue; - break; - case '+': /* Opcode extension character. */ switch (*++args) { @@ -12656,7 +12647,7 @@ mips_ip (char *str, struct mips_cl_insn *ip) case 'X': /* MDMX destination register. */ case 'Y': /* MDMX source register. */ case 'Z': /* MDMX target register. */ - is_mdmx = 1; + is_mdmx = !(insn->membership & INSN_5400); case 'W': gas_assert (!mips_opts.micromips); case 'D': /* Floating point destination register. */ @@ -12712,6 +12703,11 @@ mips_ip (char *str, struct mips_cl_insn *ip) /* This is like 'Z', but also needs to fix the MDMX vector/scalar select bits. Note that the scalar immediate case is handled above. */ + if ((ip->insn_mo->membership & INSN_5400) + && strcmp (insn->name, "rzu.ob") == 0) + as_bad (_("Operand %d of `%s' must be an immediate"), + argnum, ip->insn_mo->name); + if (*s == '[') { int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); @@ -12734,7 +12730,13 @@ mips_ip (char *str, struct mips_cl_insn *ip) s++; } else - { + { + if ((ip->insn_mo->membership & INSN_5400) + && (strcmp (insn->name, "sll.ob") == 0 + || strcmp (insn->name, "srl.ob") == 0)) + as_bad (_("Operand %d of `%s' must be scalar"), + argnum, ip->insn_mo->name); + if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH << OP_SH_VSEL); diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index bf440eb857..e918828af1 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + * gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test. + * gas/mips/mips.exp: Run it. + +2013-07-07 Richard Sandiford <rdsandiford@googlemail.com> + * gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names for LWC0 and SWC0. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index b7538deab5..a1254d930b 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -707,6 +707,7 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "vr4120-2" run_dump_test "vr4130" run_dump_test "vr5400" + run_list_test "vr5400-ill" "-march=vr5400" run_dump_test "vr5500" run_dump_test "rm7000" run_dump_test "perfcount" diff --git a/gas/testsuite/gas/mips/vr5400-ill.l b/gas/testsuite/gas/mips/vr5400-ill.l new file mode 100644 index 0000000000..1351947a3c --- /dev/null +++ b/gas/testsuite/gas/mips/vr5400-ill.l @@ -0,0 +1,13 @@ +.*: Assembler messages: +.*:3: Error: Operand 3 of `sll.ob' must be scalar +.*:7: Error: Operand 3 of `srl.ob' must be scalar +.*:10: Error: Operand 2 of `rzu.ob' must be an immediate +.*:11: Error: Operand 2 of `rzu.ob' must be an immediate +.*:14: Error: Illegal operands `add.ob \$v2,\$f4,\$f6' +.*:15: Error: Illegal operands `add.ob \$f2,\$v4,\$f6' +.*:16: Error: Illegal operands `add.ob \$f2,\$f4,\$v6' +.*:17: Error: Illegal operands `add.ob \$v2,\$v4,\$v6' +.*:20: Error: Illegal operands `add.ob \$v2,\$f4,\$f6\[1\]' +.*:21: Error: Illegal operands `add.ob \$f2,\$v4,\$f6\[1\]' +.*:22: Error: Illegal operands `add.ob \$f2,\$f4,\$v6\[1\]' +.*:23: Error: Illegal operands `add.ob \$v2,\$v4,\$v6\[1\]' diff --git a/gas/testsuite/gas/mips/vr5400-ill.s b/gas/testsuite/gas/mips/vr5400-ill.s new file mode 100644 index 0000000000..88a48da4c2 --- /dev/null +++ b/gas/testsuite/gas/mips/vr5400-ill.s @@ -0,0 +1,23 @@ + sll.ob $f2,$f4,4 + sll.ob $f2,$f4,$f6[1] + sll.ob $f2,$f4,$f6 + + srl.ob $f2,$f4,4 + srl.ob $f2,$f4,$f6[1] + srl.ob $f2,$f4,$f6 + + rzu.ob $f2,4 + rzu.ob $f2,$f6[1] + rzu.ob $f2,$f6 + + add.ob $f2,$f4,$f6 + add.ob $v2,$f4,$f6 + add.ob $f2,$v4,$f6 + add.ob $f2,$f4,$v6 + add.ob $v2,$v4,$v6 + + add.ob $f2,$f4,$f6[1] + add.ob $v2,$f4,$f6[1] + add.ob $f2,$v4,$f6[1] + add.ob $f2,$f4,$v6[1] + add.ob $v2,$v4,$v6[1] |