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* Add AMD bdver4 support.sekanath2013-09-301-0/+2
* Add Intel AVX-512 supportH.J. Lu2013-07-261-2/+33
* Support Intel SHAH.J. Lu2013-07-251-0/+3
* Support Intel MPXH.J. Lu2013-07-241-0/+7
* gas/sekanath2013-05-151-1/+1
* Implement Intel SMAP instructionsH.J. Lu2013-02-191-0/+3
* Add OPERAND_TYPE_IMM32_64H.J. Lu2013-01-161-0/+2
* Update copyright year to 2013H.J. Lu2013-01-021-2/+2
* Add AMD bdver3 support.neggone2012-10-091-0/+2
* Add missing Cpu flags in bd and bt coresH.J. Lu2012-09-251-4/+4
* Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu2012-09-201-8/+11
* Add AMD btver1 and btver2 supportH.J. Lu2012-08-171-0/+4
* Enable FMA instructions for bdver2H.J. Lu2012-08-101-1/+1
* Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu2012-07-161-0/+9
* gas/Roland McGrath2012-06-221-8/+9
* Implement Intel Transactional Synchronization ExtensionsH.J. Lu2012-02-081-0/+7
* Add vmfuncH.J. Lu2012-01-131-0/+3
* Add initial Intel K1OM support.H.J. Lu2011-07-221-1/+4
* Support AVX Programming Reference (June, 2011).H.J. Lu2011-06-101-2/+15
* Add CpuF16C to CPU_BDVER2_FLAGS.qneill2011-06-031-1/+1
* 2011-05-10 Quentin Neill <quentin.neill@amd.com>qneill2011-05-111-0/+2
* * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bitsqneill2011-04-191-1/+1
* Add support for TBM instructions.qneill2011-01-171-0/+3
* Implement BMI instructions.H.J. Lu2011-01-051-0/+3
* Update copyright in comments to 2011.H.J. Lu2011-01-011-2/+2
* Update copyright to 2011.H.J. Lu2011-01-011-1/+1
* Add CpuNop to CPU_GENERIC64_FLAGS.H.J. Lu2010-10-161-1/+1
* Add CheckRegSize to instructions which require register size check.H.J. Lu2010-10-141-0/+1
* Don't generate multi-byte NOPs for i686.H.J. Lu2010-08-061-12/+17
* Support AVX Programming Reference (June, 2010)H.J. Lu2010-07-011-0/+12
* Update copyright.H.J. Lu2010-02-111-2/+2
* 2010-02-10 Quentin Neill <quentin.neill@amd.com>spop2010-02-111-0/+3
* 2010-02-03 Quentin Neill <quentin.neill@amd.com>spop2010-02-031-1/+1
* 2010-01-06 Quentin Neill <quentin.neill@amd.com>spop2010-01-061-0/+2
* Replace VexNDS, VexNDD and VexLWP with VexVVVV.H.J. Lu2009-12-191-3/+1
* Move Imm1 before Imm8.H.J. Lu2009-12-181-1/+1
* Remove ByteOkIntel.H.J. Lu2009-12-161-1/+0
* Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode.H.J. Lu2009-12-161-6/+1
* Replace Vex2Sources and Vex3Sources with VexSources.H.J. Lu2009-12-161-2/+1
* Remove VexW0 and VexW1. Add VexW.H.J. Lu2009-12-161-2/+1
* 2009-11-18 Sebastian Pop <sebastian.pop@amd.com>spop2009-11-181-4/+1
* 2009-11-17 Sebastian Pop <sebastian.pop@amd.com>spop2009-11-181-0/+8
* gas/H.J. Lu2009-11-121-0/+1
* 2009-11-05 Sebastian Pop <sebastian.pop@amd.com>spop2009-11-051-1/+7
* gas/H.J. Lu2009-09-241-1/+23
* Updated sources to avoid using the identifier name "new", which is aNick Clifton2009-08-291-1/+1
* bfd/H.J. Lu2009-07-251-11/+45
* gas/Jan Beulich2009-07-241-16/+39
* <gas changes>Dwarakanath Rajagopal2009-07-061-0/+3
* <gas changes>Dwarakanath Rajagopal2009-05-221-6/+0
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