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| author | Craig Topper <craig.topper@intel.com> | 2018-05-30 18:02:11 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-05-30 18:02:11 +0000 |
| commit | 35691f2512500bb48016a094cb2d3466e2bbc8a9 (patch) | |
| tree | 5e429858fae7843b62b4d5d7a7cb69d79f1f8421 /test/Headers/x86intrin-2.c | |
| parent | 3c60ee554b0c5e89f4de179ea4833880ba099119 (diff) | |
| download | clang-35691f2512500bb48016a094cb2d3466e2bbc8a9.tar.gz | |
[X86] Reduce the number of setzero intrinsics to just the set defined by the Intel Intrinsics Guide.
We had quite a few for different element sizes of integers sometimes with strange target features attached to them.
We only need a single version for each of _m128i, _m256i, and _m512i with the target feature that first introduced those types.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@333568 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Headers/x86intrin-2.c')
| -rw-r--r-- | test/Headers/x86intrin-2.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/test/Headers/x86intrin-2.c b/test/Headers/x86intrin-2.c index 9be8545a2c..e6fd7c8044 100644 --- a/test/Headers/x86intrin-2.c +++ b/test/Headers/x86intrin-2.c @@ -72,10 +72,6 @@ __mmask8 __attribute__((__target__("avx512vl"))) mm_cmpeq_epi32_mask_wrap(__m128 return _mm_cmpeq_epi32_mask(a, b); } -__m512i __attribute__((__target__("avx512bw"))) mm512_setzero_qi_wrap(void) { - return _mm512_setzero_qi(); -} - __m512i __attribute__((__target__("avx512dq"))) mm512_mullo_epi64_wrap(__m512i a, __m512i b) { return _mm512_mullo_epi64(a, b); } |