diff options
| author | Yann Gautier <yann.gautier@st.com> | 2020-10-05 11:02:54 +0200 |
|---|---|---|
| committer | Yann Gautier <yann.gautier@foss.st.com> | 2021-04-21 15:05:57 +0200 |
| commit | 4324a14bf548f5c56edc48128aba1aca0da2edf5 (patch) | |
| tree | 04388b3318cc52a2109733f20ace432f3a653a6e /bl32/sp_min | |
| parent | fb4f511f9b454ea9e03f6391790693a834d8a830 (diff) | |
| download | arm-trusted-firmware-4324a14bf548f5c56edc48128aba1aca0da2edf5.tar.gz | |
Add PIE support for AARCH32
Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just
stubbed with _pie_fixup_size=0.
The changes are an adaptation for AARCH32 on what has been done for
PIE support on AARCH64.
The RELA_SECTION is redefined for AARCH32, as the created section is
.rel.dyn and the symbols are .rel*.
Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Diffstat (limited to 'bl32/sp_min')
| -rw-r--r-- | bl32/sp_min/aarch32/entrypoint.S | 13 | ||||
| -rw-r--r-- | bl32/sp_min/sp_min.ld.S | 7 |
2 files changed, 15 insertions, 5 deletions
diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S index f3a1e440b..39f1065f0 100644 --- a/bl32/sp_min/aarch32/entrypoint.S +++ b/bl32/sp_min/aarch32/entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,6 +23,8 @@ .globl sp_min_handle_smc .globl sp_min_handle_fiq +#define FIXUP_SIZE ((BL32_LIMIT) - (BL32_BASE)) + .macro route_fiq_to_sp_min reg /* ----------------------------------------------------- * FIQs are secure interrupts trapped by Monitor and non @@ -87,7 +89,8 @@ func sp_min_entrypoint _secondary_cold_boot=0 \ _init_memory=0 \ _init_c_runtime=1 \ - _exception_vectors=sp_min_vector_table + _exception_vectors=sp_min_vector_table \ + _pie_fixup_size=FIXUP_SIZE /* --------------------------------------------------------------------- * Relay the previous bootloader's arguments to the platform layer @@ -106,7 +109,8 @@ func sp_min_entrypoint _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ _init_memory=1 \ _init_c_runtime=1 \ - _exception_vectors=sp_min_vector_table + _exception_vectors=sp_min_vector_table \ + _pie_fixup_size=FIXUP_SIZE /* --------------------------------------------------------------------- * For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader @@ -306,7 +310,8 @@ func sp_min_warm_entrypoint _secondary_cold_boot=0 \ _init_memory=0 \ _init_c_runtime=0 \ - _exception_vectors=sp_min_vector_table + _exception_vectors=sp_min_vector_table \ + _pie_fixup_size=0 /* * We're about to enable MMU and participate in PSCI state coordination. diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S index f202c7ada..475affae4 100644 --- a/bl32/sp_min/sp_min.ld.S +++ b/bl32/sp_min/sp_min.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -92,6 +92,7 @@ SECTIONS __RW_START__ = . ; DATA_SECTION >RAM + RELA_SECTION >RAM #ifdef BL32_PROGBITS_LIMIT ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.") @@ -141,5 +142,9 @@ SECTIONS __BL32_END__ = .; + /DISCARD/ : { + *(.dynsym .dynstr .hash .gnu.hash) + } + ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.") } |