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| author | Andre Przywara <andre.przywara@arm.com> | 2022-03-24 11:56:30 +0000 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2022-07-19 11:45:10 +0100 |
| commit | 5016ee44a740127f7865dc26ed0efbbff1481c7e (patch) | |
| tree | 11cd560aec9f9b628e5b98d823f1cfafe6d39c17 /fdts | |
| parent | 30df8904d0f6973bbce1ecb51f14c1e4725ddf0b (diff) | |
| download | arm-trusted-firmware-5016ee44a740127f7865dc26ed0efbbff1481c7e.tar.gz | |
fix(morello): dts: fix SMMU IRQ ordering
The official SMMUv3 DT bindings require a certain order of the
interrupts, Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: iommu@4f400000: interrupt-names: 'oneOf' conditional failed, one must be fixed:
['eventq', 'priq', 'cmdq-sync', 'gerror'] is too long
'combined' was expected
'gerror' was expected
'priq' was expected
'cmdq-sync' was expected
From schema: Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
============
Swap the order of the interrupt-names and their corresponding interrupts
values to improve bindings compliance.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I2110b8509593a4f1aadff11bd518ec4a0f3f5d3c
Diffstat (limited to 'fdts')
| -rw-r--r-- | fdts/morello-soc.dts | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/fdts/morello-soc.dts b/fdts/morello-soc.dts index 2f9865bd9..64742f167 100644 --- a/fdts/morello-soc.dts +++ b/fdts/morello-soc.dts @@ -79,10 +79,10 @@ compatible = "arm,smmu-v3"; reg = <0 0x4f400000 0 0x40000>; interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; msi-parent = <&its2 0>; #iommu-cells = <1>; dma-coherent; @@ -115,10 +115,10 @@ compatible = "arm,smmu-v3"; reg = <0 0x4f000000 0 0x40000>; interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; msi-parent = <&its1 0>; #iommu-cells = <1>; dma-coherent; |