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| author | Andre Przywara <andre.przywara@arm.com> | 2023-02-22 16:53:50 +0000 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2023-03-22 13:33:22 +0000 |
| commit | 623f6140fc8eaa547d477179b67ca2fde2720fe4 (patch) | |
| tree | 78ec3b8cbf50ecbbeedbce2f862b69c7f6b05a52 /include/arch | |
| parent | d5384b69d1180a596a48014d99e46eb4341f3455 (diff) | |
| download | arm-trusted-firmware-623f6140fc8eaa547d477179b67ca2fde2720fe4.tar.gz | |
refactor(cpufeat): align FEAT_SEL2 to new feature handling
In ARMv8.4, the EL2 exception level got added to the secure world.
Adapt and rename the existing is_armv8_4_sel2_present() function, to
align its handling with the other CPU features.
Change-Id: If11e1942fdeb63c63f36ab9e89be810347d1a952
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'include/arch')
| -rw-r--r-- | include/arch/aarch64/arch_features.h | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 72927fbf9..03b005d1e 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -113,10 +113,22 @@ static inline unsigned int get_armv8_5_mte_support(void) ID_AA64PFR1_EL1_MTE_MASK); } -static inline bool is_armv8_4_sel2_present(void) +static inline unsigned int read_feat_sel2_id_field(void) { - return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SEL2_SHIFT) & - ID_AA64PFR0_SEL2_MASK) == 1ULL; + return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2); +} + +static inline bool is_feat_sel2_supported(void) +{ + if (ENABLE_FEAT_SEL2 == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_FEAT_SEL2 == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_sel2_id_field() != 0U; } static inline unsigned int read_feat_twed_id_field(void) |